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Preamble

This list of registers is generated from the GPU related code published by Broadcom (http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz) by the script in https://github.com/msperl/rpi-registers which parses the header files in the source code by including:

brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/register_map.h
brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/register_map_macros.h

and transforms the defined macros into different formats (html, markdown, mediawiki)

The transformation tries to follow the formatting of the Broadcom peripheral document and also tries to provide "some consistent" structuring for each Register section right from the start.

Register Regions

register region	base address	description
A2W	0x7e102000
APERF0	0x7e009800
APERF1	0x7ee08000
APHY_CSR	0x7ee06000
ASB	0x7e00a000
AVE_IN	0x7e910000
AVE_OUT	0x7e240000
CAM0	0x7e800000
CAM1	0x7e801000
CCP2TX	0x7e001000
CM	0x7e101000
CMI	0x7e802000
CPG	0x7e211000
DMA	0x7e007fe0
DMA0	0x7e007000
DMA1	0x7e007100
DMA2	0x7e007200
DMA3	0x7e007300
DMA4	0x7e007400
DMA5	0x7e007500
DMA6	0x7e007600
DMA7	0x7e007700
DMA8	0x7e007800
DMA9	0x7e007900
DMA10	0x7e007a00
DMA11	0x7e007b00
DMA12	0x7e007c00
DMA13	0x7e007d00
DMA14	0x7e007e00
DMA15	0x7ee05000
DPHY_CSR	0x7ee07000
DPI	0x7e208000
DSI0	0x7e209000
DSI1	0x7e700000
EMMC	0x7e300000
FPGA	0x7e20b600
FPGA_A0	0x7e213000
FPGA_B0	0x7e214000
FPGA_MB	0x7e20b700
GP	0x7e200000
H264	0x7f000000
HD	0x7e808000
HDCP	0x7e809000
HDMI	0x7e902000
I2C0	0x7e205000
I2C1	0x7e804000
I2C2	0x7e805000
I2C_SPI_SLV	0x7e214000
IC0	0x7e002000
IC1	0x7e002800
ISP	0x7ea00000
JP	0x7e005000
L1	0x7ee02000
L2	0x7ee01000
MPHI	0x7e006000
MS	0x7e000000
NU	0x7e008000
OTP	0x7e20f000
PCM	0x7e203000
PIARBCTL	0x7e80a000
PIXELVALVE0	0x7e206000
PIXELVALVE1	0x7e207000
PIXELVALVE2	0x7e807000
PM	0x7e100000
PRM	0x7e20d000
PWM	0x7e20c000
RNG	0x7e104000
SCALER	0x7e400000
SD	0x7ee00000
SH	0x7e202000
SLIM	0x7e210000
SMI	0x7e600000
SPI	0x7e204000
ST	0x7e003000
SYSAC	0x7e009000
TB	0x7e20b000
TE	0x7e20e000
TS	0x7e212000
TXP	0x7e004000
USB	0x7e980000
V3D	0x7ec00000
VEC	0x7e806000
VPU_ARB_CTRL	0x7ee04000

Unknown Definitions

These defines should get moved to the correct sections - maybe also copying the defines themselves from the sources.

define	type	description
`ACIS_DMA`	UNKNOWN
`AC_HUFFTABLE_OFFSET`	MACRO
`AC_MAXCTABLE_OFFSET`	MACRO
`AC_OSETTABLE_OFFSET`	MACRO
`ADC_DMA`	UNKNOWN
`ADDRESS_EXTERNAL`	MACRO
`ALIAS_ANY_NONALLOCATING`	MACRO
`ALIAS_COHERENT`	MACRO
`ALIAS_DIRECT`	MACRO
`ALIAS_NORMAL`	MACRO
`ALIAS_STREAMING`	MACRO
`AM_DB_MEMPRI`	UNKNOWN
`AM_DB_PERPRI`	UNKNOWN
`AM_HO_MEMPRI`	UNKNOWN
`AM_HO_PERPRI`	UNKNOWN
`AM_HVSM_PRI`	UNKNOWN
`AM_VP_L2_PRI`	UNKNOWN
`AM_VP_PERPRI`	UNKNOWN
`AM_VP_UC_PRI`	UNKNOWN
`BIT_STREAM_DMA`	UNKNOWN
`BOOTROM_BASE_ADDRESS`	UNKNOWN
`BOOTROM_BRCTL`	UNKNOWN
`BOOTROM_RAM_LENGTH`	UNKNOWN
`BOOTROM_RAM_START`	UNKNOWN
`BOOTROM_ROM_LENGTH`	UNKNOWN
`BOOTROM_ROM_START`	UNKNOWN
`CAM_DMA`	UNKNOWN
`CDP_DEBUG0`	UNKNOWN
`CDP_DEBUG1`	UNKNOWN
`CDP_PHYC`	UNKNOWN
`CDP_PHYTSTDAT`	UNKNOWN
`CGMSAE_BOT_CONTROL`	UNKNOWN
`CGMSAE_BOT_DATA`	UNKNOWN
`CGMSAE_BOT_FORMAT`	UNKNOWN
`CGMSAE_RESET`	UNKNOWN
`CGMSAE_REVID`	UNKNOWN
`CGMSAE_TOP_CONTROL`	UNKNOWN
`CGMSAE_TOP_DATA`	UNKNOWN
`CGMSAE_TOP_FORMAT`	UNKNOWN
`CRYPTO_IP_DMA`	UNKNOWN
`CRYPTO_ISR`	UNKNOWN
`CRYPTO_ISR_RNG_INT`	UNKNOWN
`CRYPTO_OP_DMA`	UNKNOWN
`CSI2_DTOV0`	UNKNOWN
`CSI2_DTOV1`	UNKNOWN
`CSI2_DTOV_x`	MACRO
`CSI2_RBC0`	UNKNOWN
`CSI2_RBC1`	UNKNOWN
`CSI2_RBC_x`	MACRO
`CSI2_RC`	UNKNOWN
`CSI2_RC0`	UNKNOWN
`CSI2_RC1`	UNKNOWN
`CSI2_RC_x`	MACRO
`CSI2_RDEA0`	UNKNOWN
`CSI2_RDEA1`	UNKNOWN
`CSI2_RDEA_x`	MACRO
`CSI2_RDLS`	UNKNOWN
`CSI2_RDS0`	UNKNOWN
`CSI2_RDS1`	UNKNOWN
`CSI2_RDSA0`	UNKNOWN
`CSI2_RDSA1`	UNKNOWN
`CSI2_RDSA_x`	MACRO
`CSI2_RDS_x`	MACRO
`CSI2_REA0`	UNKNOWN
`CSI2_REA1`	UNKNOWN
`CSI2_REA_x`	MACRO
`CSI2_RGSP`	UNKNOWN
`CSI2_RLS0`	UNKNOWN
`CSI2_RLS1`	UNKNOWN
`CSI2_RLS_x`	MACRO
`CSI2_RPC0`	UNKNOWN
`CSI2_RPC1`	UNKNOWN
`CSI2_RPC_x`	MACRO
`CSI2_RS`	UNKNOWN
`CSI2_RS0`	UNKNOWN
`CSI2_RS1`	UNKNOWN
`CSI2_RSA0`	UNKNOWN
`CSI2_RSA1`	UNKNOWN
`CSI2_RSA_x`	MACRO
`CSI2_RS_x`	MACRO
`CSI2_RWP0`	UNKNOWN
`CSI2_RWP1`	UNKNOWN
`CSI2_RWP_x`	MACRO
`CSI2_SRST`	UNKNOWN
`CSI2_THSCKTO`	UNKNOWN
`CSI2_THSSET`	UNKNOWN
`CSI2_THSSTO`	UNKNOWN
`CSI2_TREN`	UNKNOWN
`D1CACHE_BASE`	UNKNOWN
`DC_HUFFTABLE_OFFSET`	MACRO
`DC_MAXCTABLE_OFFSET`	MACRO
`DC_OSETTABLE_OFFSET`	MACRO
`DISP_DMA`	UNKNOWN
`DSI2_DMA`	UNKNOWN
`DSI_AFEC0`	UNKNOWN
`DSI_AFEC1`	UNKNOWN
`DSI_CMD_DATA_FIFO`	UNKNOWN
`DSI_CMD_PKTC`	UNKNOWN
`DSI_CMD_PKTH`	UNKNOWN
`DSI_CTRL`	UNKNOWN
`DSI_DISP0_CTRL`	UNKNOWN
`DSI_DISP1_CTRL`	UNKNOWN
`DSI_DMA`	UNKNOWN
`DSI_HSTX_TO_CNT`	UNKNOWN
`DSI_HS_CLT0`	UNKNOWN
`DSI_HS_CLT1`	UNKNOWN
`DSI_HS_CLT2`	UNKNOWN
`DSI_HS_DLT3`	UNKNOWN
`DSI_HS_DLT4`	UNKNOWN
`DSI_HS_DLT5`	UNKNOWN
`DSI_INT_ENABLE`	UNKNOWN
`DSI_INT_STATUS`	UNKNOWN
`DSI_LPRX_TO_CNT`	UNKNOWN
`DSI_LP_DLT6`	UNKNOWN
`DSI_LP_DLT7`	UNKNOWN
`DSI_PHY_CONTROL`	UNKNOWN
`DSI_PIX_FIFO`	UNKNOWN
`DSI_PR_TO_CNT`	UNKNOWN
`DSI_RX1_PKTH`	UNKNOWN
`DSI_RX2_PKTH`	UNKNOWN
`DSI_STAT`	UNKNOWN
`DSI_TA_TO_CNT`	UNKNOWN
`DSI_TST_MON`	UNKNOWN
`DSI_TST_SEL`	UNKNOWN
`GROPCTR_FBC_CZ_CLRFLG_FETCHES`	UNKNOWN
`GROPCTR_FBC_CZ_EVICTIONS`	UNKNOWN
`GROPCTR_FBC_CZ_FETCHES`	UNKNOWN
`GROPCTR_FBC_CZ_FETCH_STALLS`	UNKNOWN
`GROPCTR_FBC_CZ_FE_DISCARDED`	UNKNOWN
`GROPCTR_FBC_CZ_FE_HITS`	UNKNOWN
`GROPCTR_FBC_CZ_FE_LINE_REQS`	UNKNOWN
`GROPCTR_FBC_CZ_FE_MISSES`	UNKNOWN
`GROPCTR_FBC_CZ_FE_QUAD_REQS`	UNKNOWN
`GROPCTR_FBC_CZ_FE_UNUSED`	UNKNOWN
`GROPCTR_FBC_CZ_LINE_FLUSHES`	UNKNOWN
`GROPCTR_FBC_CZ_PBE_HITS`	UNKNOWN
`GROPCTR_FBC_CZ_PBE_MISSES`	UNKNOWN
`GROPCTR_FBC_CZ_PBE_REQS`	UNKNOWN
`GROPCTR_FBC_CZ_PBE_STALLS`	UNKNOWN
`GROPCTR_FBC_CZ_UM_STALLS`	UNKNOWN
`GROPCTR_FBC_EZ_CLRFLG_FETCHES`	UNKNOWN
`GROPCTR_FBC_EZ_EVICTIONS`	UNKNOWN
`GROPCTR_FBC_EZ_FETCHES`	UNKNOWN
`GROPCTR_FBC_EZ_FETCH_STALLS`	UNKNOWN
`GROPCTR_FBC_EZ_FE_FETCHES`	UNKNOWN
`GROPCTR_FBC_EZ_FE_HITS`	UNKNOWN
`GROPCTR_FBC_EZ_FE_MISSES`	UNKNOWN
`GROPCTR_FBC_EZ_FE_REQS`	UNKNOWN
`GROPCTR_FBC_EZ_LINE_FLUSHES`	UNKNOWN
`GROPCTR_FBC_EZ_PBE_HITS`	UNKNOWN
`GROPCTR_FBC_EZ_PBE_MISSES`	UNKNOWN
`GROPCTR_FBC_EZ_PBE_REQS`	UNKNOWN
`GROPCTR_FBC_EZ_PBE_STALLS`	UNKNOWN
`GROPCTR_FBC_EZ_UM_STALLS`	UNKNOWN
`GROPCTR_FEINVALIDPIXELS`	UNKNOWN
`GROPCTR_FEPEZIDLE`	UNKNOWN
`GROPCTR_FEPEZRDY`	UNKNOWN
`GROPCTR_FESPMRDY`	UNKNOWN
`GROPCTR_FESPMSTALL`	UNKNOWN
`GROPCTR_FESTALLPREFETCH`	UNKNOWN
`GROPCTR_FEVALIDPRIMS`	UNKNOWN
`GROPCTR_FEVALIDQUADS`	UNKNOWN
`GROPCTR_FEZCULLEDQUADS`	UNKNOWN
`GROPCTR_FOVCLIPPEDPRIMS`	UNKNOWN
`GROPCTR_FOVCULLEDPRIMS`	UNKNOWN
`GROPCTR_NOFEPIXELPRIMS`	UNKNOWN
`GROPCTR_PBE_DEPTH_TEST_FAIL`	UNKNOWN
`GROPCTR_PBE_DPTH_STCL_PASS`	UNKNOWN
`GROPCTR_PBE_FE_STALLS`	UNKNOWN
`GROPCTR_PBE_STCL_TEST_FAIL`	UNKNOWN
`GROPCTR_REVCULLEDPRIMS`	UNKNOWN
`GROPCTR_TU0_AXI_REQ_FIFO_FULL`	UNKNOWN
`GROPCTR_TU0_CACHE_ACCESSES`	UNKNOWN
`GROPCTR_TU0_CACHE_MISSES`	UNKNOWN
`GROPCTR_TU0_CACHE_RCV_WAITS`	UNKNOWN
`GROPCTR_TU0_CACHE_REQ_STALLS`	UNKNOWN
`GROPCTR_TU0_CACHE_STALLS`	UNKNOWN
`GROPCTR_TU0_SAME_BANK_STALL`	UNKNOWN
`GROPCTR_TU0_SAME_SET_STALL`	UNKNOWN
`GROPCTR_TU1_AXI_REQ_FIFO_FULL`	UNKNOWN
`GROPCTR_TU1_CACHE_ACCESSES`	UNKNOWN
`GROPCTR_TU1_CACHE_MISSES`	UNKNOWN
`GROPCTR_TU1_CACHE_RCV_WAITS`	UNKNOWN
`GROPCTR_TU1_CACHE_REQ_STALLS`	UNKNOWN
`GROPCTR_TU1_CACHE_STALLS`	UNKNOWN
`GROPCTR_TU1_SAME_BANK_STALL`	UNKNOWN
`GROPCTR_TU1_SAME_SET_STALL`	UNKNOWN
`GRP_FDBGB`	UNKNOWN
`GRP_FDBGO`	UNKNOWN
`GRP_FDBGR`	UNKNOWN
`GRP_FDBGS`	UNKNOWN
`GRP_SDBG0`	UNKNOWN
`GRS_DBGE`	UNKNOWN
`GRTMPM0_BASE`	UNKNOWN
`GRTMPM1_BASE`	UNKNOWN
`GRTMPM_MASK`	UNKNOWN
`GR_FBC_ADDR_MASK`	UNKNOWN
`GR_FBC_BASE`	UNKNOWN
`GR_FBC_DEBUG_ADDR_MASK`	UNKNOWN
`GR_FBC_DEBUG_BASE`	UNKNOWN
`GR_PPL_ADDR_MASK`	UNKNOWN
`GR_PPL_BASE`	UNKNOWN
`GR_PPL_DEBUG_ADDR_MASK`	UNKNOWN
`GR_PPL_DEBUG_BASE`	UNKNOWN
`GR_PSE_ADDR_MASK`	UNKNOWN
`GR_PSE_BASE`	UNKNOWN
`GR_PSE_DEBUG_ADDR_MASK`	UNKNOWN
`GR_PSE_DEBUG_BASE`	UNKNOWN
`GR_SYSTEM_BASE`	UNKNOWN
`GR_SYSTEM_DEBUG_BASE`	UNKNOWN
`GR_TU_ADDR_MASK`	UNKNOWN
`GR_TU_BASE0`	UNKNOWN
`GR_TU_BASE1`	UNKNOWN
`GR_TU_BASE2`	UNKNOWN
`GR_TU_BASE3`	UNKNOWN
`GR_TU_BASE4`	UNKNOWN
`GR_TU_BASE5`	UNKNOWN
`GR_TU_BASE6`	UNKNOWN
`GR_TU_BASE7`	UNKNOWN
`GR_TU_DBG_BASE`	UNKNOWN
`GR_TU_UNIT_MASK`	UNKNOWN
`GR_UNIFORM_ADDR_MASK`	UNKNOWN
`GR_UNIFORM_BASE`	UNKNOWN
`GR_UNIFORM_SIZE`	UNKNOWN
`GR_VCACHE_ADDR_MASK`	UNKNOWN
`GR_VCACHE_BASE`	UNKNOWN
`GR_VCACHE_SIZE`	UNKNOWN
`GR_VCD_ADDR_MASK`	UNKNOWN
`GR_VCD_BASE`	UNKNOWN
`GR_VCM_ADDR_MASK`	UNKNOWN
`GR_VCM_BASE`	UNKNOWN
`GR_VCM_CI_ADDR_MASK`	UNKNOWN
`GR_VCM_CI_BASE`	UNKNOWN
`GR_VPM_VRFCFG_ADDR_MASK`	UNKNOWN
`GR_VPM_VRFCFG_BASE`	UNKNOWN
`HW_POINTER_TO_ADDRESS`	MACRO
`HW_REGISTER_RO`	MACRO
`HW_REGISTER_RW`	MACRO
`I1CACHE_BASE`	UNKNOWN
`I2CA_0`	UNKNOWN
`I2CA_1`	UNKNOWN
`I2CA_2`	UNKNOWN
`I2CA_3`	UNKNOWN
`I2CA_x`	MACRO
`I2CCLKT_0`	UNKNOWN
`I2CCLKT_1`	UNKNOWN
`I2CCLKT_2`	UNKNOWN
`I2CCLKT_3`	UNKNOWN
`I2CCLKT_x`	MACRO
`I2CC_0`	UNKNOWN
`I2CC_1`	UNKNOWN
`I2CC_2`	UNKNOWN
`I2CC_3`	UNKNOWN
`I2CC_x`	MACRO
`I2CDEL_0`	UNKNOWN
`I2CDEL_1`	UNKNOWN
`I2CDEL_2`	UNKNOWN
`I2CDEL_3`	UNKNOWN
`I2CDEL_x`	MACRO
`I2CDIV_0`	UNKNOWN
`I2CDIV_1`	UNKNOWN
`I2CDIV_2`	UNKNOWN
`I2CDIV_3`	UNKNOWN
`I2CDIV_x`	MACRO
`I2CDLEN_0`	UNKNOWN
`I2CDLEN_1`	UNKNOWN
`I2CDLEN_2`	UNKNOWN
`I2CDLEN_3`	UNKNOWN
`I2CDLEN_x`	MACRO
`I2CFIFO_0`	UNKNOWN
`I2CFIFO_1`	UNKNOWN
`I2CFIFO_2`	UNKNOWN
`I2CFIFO_3`	UNKNOWN
`I2CFIFO_x`	MACRO
`I2CS_0`	UNKNOWN
`I2CS_1`	UNKNOWN
`I2CS_2`	UNKNOWN
`I2CS_3`	UNKNOWN
`I2CS_x`	MACRO
`IC_0`	UNKNOWN
`IC_1`	UNKNOWN
`IC_MASK0`	UNKNOWN
`IC_VADDR`	UNKNOWN
`IFORCE0_0`	UNKNOWN
`IFORCE0_1`	UNKNOWN
`IFORCE1_0`	UNKNOWN
`IFORCE1_1`	UNKNOWN
`IMASK0_0`	UNKNOWN
`IMASK0_1`	UNKNOWN
`IMASK1_0`	UNKNOWN
`IMASK1_1`	UNKNOWN
`IMASK2_0`	UNKNOWN
`IMASK2_1`	UNKNOWN
`IMASK3_0`	UNKNOWN
`IMASK3_1`	UNKNOWN
`IMASK4_0`	UNKNOWN
`IMASK4_1`	UNKNOWN
`IMASK5_0`	UNKNOWN
`IMASK5_1`	UNKNOWN
`IMASK6_0`	UNKNOWN
`IMASK6_1`	UNKNOWN
`IMASK7_0`	UNKNOWN
`IMASK7_1`	UNKNOWN
`IMASKx_0`	MACRO
`IMASKx_1`	MACRO
`INTERRUPT_3D`	UNKNOWN
`INTERRUPT_ADC`	UNKNOWN
`INTERRUPT_CCP2`	UNKNOWN
`INTERRUPT_CDP`	UNKNOWN
`INTERRUPT_CODEC0`	UNKNOWN
`INTERRUPT_CODEC1`	UNKNOWN
`INTERRUPT_CODEC2`	UNKNOWN
`INTERRUPT_CRYPTO`	UNKNOWN
`INTERRUPT_CSI2`	UNKNOWN
`INTERRUPT_DMA0`	UNKNOWN
`INTERRUPT_DMA1`	UNKNOWN
`INTERRUPT_DMA10`	UNKNOWN
`INTERRUPT_DMA11`	UNKNOWN
`INTERRUPT_DMA12`	UNKNOWN
`INTERRUPT_DMA13`	UNKNOWN
`INTERRUPT_DMA14`	UNKNOWN
`INTERRUPT_DMA15`	UNKNOWN
`INTERRUPT_DMA2`	UNKNOWN
`INTERRUPT_DMA3`	UNKNOWN
`INTERRUPT_DMA4`	UNKNOWN
`INTERRUPT_DMA5`	UNKNOWN
`INTERRUPT_DMA6`	UNKNOWN
`INTERRUPT_DMA7`	UNKNOWN
`INTERRUPT_DMA8`	UNKNOWN
`INTERRUPT_DMA9`	UNKNOWN
`INTERRUPT_DSI0`	UNKNOWN
`INTERRUPT_DUMMY`	UNKNOWN
`INTERRUPT_EXCEPTION_NUM`	UNKNOWN
`INTERRUPT_EXCEPTION_OFFSET`	UNKNOWN
`INTERRUPT_GPIO0`	UNKNOWN
`INTERRUPT_GPIO1`	UNKNOWN
`INTERRUPT_GPIO2`	UNKNOWN
`INTERRUPT_GPION`	UNKNOWN
`INTERRUPT_HARDINT_NUM`	UNKNOWN
`INTERRUPT_HARDINT_OFFSET`	UNKNOWN
`INTERRUPT_HDMI0`	UNKNOWN
`INTERRUPT_HDMI1`	UNKNOWN
`INTERRUPT_HOSTINTERFACE`	UNKNOWN
`INTERRUPT_HOSTPORT`	UNKNOWN
`INTERRUPT_HW_NUM`	UNKNOWN
`INTERRUPT_HW_OFFSET`	UNKNOWN
`INTERRUPT_I2C`	UNKNOWN
`INTERRUPT_I2SPCM`	UNKNOWN
`INTERRUPT_ISP`	UNKNOWN
`INTERRUPT_JPEG`	UNKNOWN
`INTERRUPT_MULTICORESYNC0`	UNKNOWN
`INTERRUPT_MULTICORESYNC1`	UNKNOWN
`INTERRUPT_MULTICORESYNC2`	UNKNOWN
`INTERRUPT_MULTICORESYNC3`	UNKNOWN
`INTERRUPT_PARALLELCAMERA`	UNKNOWN
`INTERRUPT_PIXELVALVE0`	UNKNOWN
`INTERRUPT_PIXELVALVE1`	UNKNOWN
`INTERRUPT_PLL`	UNKNOWN
`INTERRUPT_SDCARDHOST`	UNKNOWN
`INTERRUPT_SDIO`	UNKNOWN
`INTERRUPT_SLIMBUS`	UNKNOWN
`INTERRUPT_SMI`	UNKNOWN
`INTERRUPT_SOFTINT_NUM`	UNKNOWN
`INTERRUPT_SOFTINT_OFFSET`	UNKNOWN
`INTERRUPT_SPARE1`	UNKNOWN
`INTERRUPT_SPARE2`	UNKNOWN
`INTERRUPT_SPARE3`	UNKNOWN
`INTERRUPT_SPARE4`	UNKNOWN
`INTERRUPT_SPARE5`	UNKNOWN
`INTERRUPT_SPI`	UNKNOWN
`INTERRUPT_SW_NUM`	UNKNOWN
`INTERRUPT_SW_OFFSET`	UNKNOWN
`INTERRUPT_TIMER0`	UNKNOWN
`INTERRUPT_TIMER1`	UNKNOWN
`INTERRUPT_TIMER2`	UNKNOWN
`INTERRUPT_TIMER3`	UNKNOWN
`INTERRUPT_TRANSPOSER`	UNKNOWN
`INTERRUPT_UART`	UNKNOWN
`INTERRUPT_USB`	UNKNOWN
`INTERRUPT_VEC`	UNKNOWN
`INTERRUPT_VECTOR_BASE`	UNKNOWN
`INTERRUPT_VIDEOSCALER`	UNKNOWN
`INT_CTL_BASE_ADDR1`	UNKNOWN
`IPROFILE_0`	UNKNOWN
`IPROFILE_1`	UNKNOWN
`ISRC0_0`	UNKNOWN
`ISRC0_1`	UNKNOWN
`ISRC1_0`	UNKNOWN
`ISRC1_1`	UNKNOWN
`IS_0`	UNKNOWN
`IS_1`	UNKNOWN
`IS_ALIAS_COHERENT`	MACRO
`IS_ALIAS_DIRECT`	MACRO
`IS_ALIAS_NONALLOCATING`	MACRO
`IS_ALIAS_NORMAL`	MACRO
`IS_ALIAS_STREAMING`	MACRO
`IVADDR_0`	UNKNOWN
`IVADDR_1`	UNKNOWN
`IWAKEUP_0`	UNKNOWN
`IWAKEUP_1`	UNKNOWN
`JCTRL_FLUSH`	UNKNOWN
`JCTRL_MODE`	UNKNOWN
`JCTRL_RESET`	UNKNOWN
`JCTRL_START`	UNKNOWN
`JCTRL_STUFF`	UNKNOWN
`JDCCTRL_DCCOMP_MASK`	UNKNOWN
`JDCCTRL_DISDC`	UNKNOWN
`JDCCTRL_SETDC`	MACRO
`JHADDR_TABLEF`	UNKNOWN
`JICST_CDONE`	UNKNOWN
`JICST_ERR`	UNKNOWN
`JICST_INTCD`	UNKNOWN
`JICST_INTE`	UNKNOWN
`JICST_INTM`	UNKNOWN
`JICST_INTSD`	UNKNOWN
`JICST_MARKER`	UNKNOWN
`JICST_SDONE`	UNKNOWN
`JMCTRL_AC_TAB`	MACRO
`JMCTRL_CMP`	MACRO
`JMCTRL_DC_TAB`	MACRO
`JMCTRL_NUMCMP`	UNKNOWN
`JMCTRL_UNUSED_BITS`	UNKNOWN
`MAX_DMA_NUM`	UNKNOWN
`MAX_DMA_SUB`	UNKNOWN
`MAX_EXCEPTION_NUM`	UNKNOWN
`MAX_GPIO_NUM`	UNKNOWN
`MAX_TIMER_NUM`	UNKNOWN
`MULTICORE_SYNC_ICCLR_0`	UNKNOWN
`MULTICORE_SYNC_ICCLR_1`	UNKNOWN
`MULTICORE_SYNC_ICSET_0`	UNKNOWN
`MULTICORE_SYNC_ICSET_1`	UNKNOWN
`MULTICORE_SYNC_IREQ_0`	UNKNOWN
`MULTICORE_SYNC_IREQ_1`	UNKNOWN
`MULTICORE_SYNC_MBOX_0`	UNKNOWN
`MULTICORE_SYNC_MBOX_1`	UNKNOWN
`MULTICORE_SYNC_MBOX_2`	UNKNOWN
`MULTICORE_SYNC_MBOX_3`	UNKNOWN
`MULTICORE_SYNC_MBOX_4`	UNKNOWN
`MULTICORE_SYNC_MBOX_5`	UNKNOWN
`MULTICORE_SYNC_MBOX_6`	UNKNOWN
`MULTICORE_SYNC_MBOX_7`	UNKNOWN
`MULTICORE_SYNC_MBOX_MASK`	MACRO
`MULTICORE_SYNC_NUM_SEMAPHORES`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK`	MACRO
`MULTICORE_SYNC_SEMA_MASK_0`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_1`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_10`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_11`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_12`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_13`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_14`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_15`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_16`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_17`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_18`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_19`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_2`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_20`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_21`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_22`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_23`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_24`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_25`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_26`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_27`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_28`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_29`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_3`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_30`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_31`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_4`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_5`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_6`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_7`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_8`	UNKNOWN
`MULTICORE_SYNC_SEMA_MASK_9`	UNKNOWN
`MULTICORE_SYNC_SEMA_STATUS`	UNKNOWN
`MULTICORE_SYNC_VPU_SEMA_0`	UNKNOWN
`MULTICORE_SYNC_VPU_SEMA_1`	UNKNOWN
`MULTICORE_SYNC_VPU_SEMA_STATUS`	UNKNOWN
`MULTICORE_SYNC_VPU_SEMA_x`	MACRO
`PIXELVALVE_C_0`	UNKNOWN
`PIXELVALVE_C_1`	UNKNOWN
`PIXELVALVE_C_x`	MACRO
`PIXELVALVE_HSYNC_0`	UNKNOWN
`PIXELVALVE_HSYNC_1`	UNKNOWN
`PIXELVALVE_HSYNC_x`	MACRO
`PIXELVALVE_INTEN_0`	UNKNOWN
`PIXELVALVE_INTEN_1`	UNKNOWN
`PIXELVALVE_INTEN_x`	MACRO
`PIXELVALVE_INTSTAT_0`	UNKNOWN
`PIXELVALVE_INTSTAT_1`	UNKNOWN
`PIXELVALVE_INTSTAT_x`	MACRO
`PIXELVALVE_STAT_0`	UNKNOWN
`PIXELVALVE_STAT_1`	UNKNOWN
`PIXELVALVE_STAT_x`	MACRO
`PIXELVALVE_VC_0`	UNKNOWN
`PIXELVALVE_VC_1`	UNKNOWN
`PIXELVALVE_VC_x`	MACRO
`PIXELVALVE_VSIZE_0`	UNKNOWN
`PIXELVALVE_VSIZE_1`	UNKNOWN
`PIXELVALVE_VSIZE_x`	MACRO
`PIXELVALVE_VSYNC_0`	UNKNOWN
`PIXELVALVE_VSYNC_1`	UNKNOWN
`PIXELVALVE_VSYNC_x`	MACRO
`RUN_ARBITER_CTRL_BASE_ADDRESS`	UNKNOWN
`SDRAM_CTRL_DMA`	UNKNOWN
`STC0_0`	UNKNOWN
`STC0_1`	UNKNOWN
`STC0_x`	MACRO
`STC1_0`	UNKNOWN
`STC1_1`	UNKNOWN
`STC1_x`	MACRO
`STC2_0`	UNKNOWN
`STC2_1`	UNKNOWN
`STC2_x`	MACRO
`STC3_0`	UNKNOWN
`STC3_1`	UNKNOWN
`STC3_x`	MACRO
`STCHI_0`	UNKNOWN
`STCHI_1`	UNKNOWN
`STCHI_x`	MACRO
`STCLO_0`	UNKNOWN
`STCLO_1`	UNKNOWN
`STCLO_x`	MACRO
`STCS_0`	UNKNOWN
`STCS_1`	UNKNOWN
`STCS_x`	MACRO
`STC_0`	UNKNOWN
`STC_1`	UNKNOWN
`STC_x`	MACRO
`SYSTEM_TIMER_BASE1`	UNKNOWN
`TE0_VSWIDTH`	UNKNOWN
`TE1_VSWIDTH`	UNKNOWN
`TH0_ADDR_MASK`	UNKNOWN
`TH0_BASE`	UNKNOWN
`TH1_ADDR_MASK`	UNKNOWN
`TH1_BASE`	UNKNOWN
`TRANSPOSER_CONTROL`	UNKNOWN
`TRANSPOSER_DIMENSIONS`	UNKNOWN
`TRANSPOSER_DST_PITCH`	UNKNOWN
`TRANSPOSER_DST_PTR`	UNKNOWN
`TRANSPOSER_PROGRESS`	UNKNOWN
`UNUSED_DMA_12`	UNKNOWN
`UNUSED_DMA_14`	UNKNOWN
`VIDEOCORE_NUM_GPIO_PINS`	UNKNOWN
`VIDEOCORE_NUM_UART_PORTS`	UNKNOWN
`VIDEO_ENC_PrimaryControl`	UNKNOWN
`VIDEO_ENC_RevID`	UNKNOWN
`VPU1_THREAD_CTRL_BASE_ADDRESS`	UNKNOWN
`VPU1_UNIFORM_MEM_BASE_ADDRESS`	UNKNOWN
`VRF_SIZE`	UNKNOWN
`WSE_CONTROL`	UNKNOWN
`WSE_RESET`	UNKNOWN
`WSE_VPS_CONTROL`	UNKNOWN
`WSE_VPS_DATA_1`	UNKNOWN
`WSE_WSS_DATA`	UNKNOWN

Register Regions

A2W

Description

TODO

Info

Name	value	description
base	`0x7e102000`
id	`0x00613277`
password	`0x5a000000`

Registers

name	address	type	width	mask	reset
`A2W_PLLA_DIG0`	`0x7e102000`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLA_DIG1`	`0x7e102004`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLA_DIG2`	`0x7e102008`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLA_DIG3`	`0x7e10200c`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLA_ANA0`	`0x7e102010`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLA_ANA1`	`0x7e102014`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLA_ANA2`	`0x7e102018`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLA_ANA3`	`0x7e10201c`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLC_DIG0`	`0x7e102020`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLC_DIG1`	`0x7e102024`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLC_DIG2`	`0x7e102028`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLC_DIG3`	`0x7e10202c`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLC_ANA0`	`0x7e102030`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLC_ANA1`	`0x7e102034`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLC_ANA2`	`0x7e102038`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLC_ANA3`	`0x7e10203c`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLD_DIG0`	`0x7e102040`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLD_DIG1`	`0x7e102044`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLD_DIG2`	`0x7e102048`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLD_DIG3`	`0x7e10204c`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLD_ANA0`	`0x7e102050`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLD_ANA1`	`0x7e102054`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLD_ANA2`	`0x7e102058`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLD_ANA3`	`0x7e10205c`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLH_DIG0`	`0x7e102060`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_DIG1`	`0x7e102064`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_DIG2`	`0x7e102068`	RW	24	`0x00ffffff`	`0x000000aa`
`A2W_PLLH_DIG3`	`0x7e10206c`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_ANA0`	`0x7e102070`	RW	24	`0x00ffffff`	`0x00d80000`
`A2W_PLLH_ANA1`	`0x7e102074`	RW	24	`0x00ffffff`	`0x00000014`
`A2W_PLLH_ANA2`	`0x7e102078`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_ANA3`	`0x7e10207c`	RW	24	`0x00ffffff`	`0000000000`
`A2W_HDMI_CTL0`	`0x7e102080`	RW	24	`0x00ffffff`	`0x00470238`
`A2W_HDMI_CTL1`	`0x7e102084`	RW	24	`0x00ffffff`	`0x00011c00`
`A2W_HDMI_CTL2`	`0x7e102088`	RW	24	`0x00ffffff`	`0x0018048e`
`A2W_HDMI_CTL3`	`0x7e10208c`	RW	24	`0x00ffffff`	`0x00000040`
`A2W_XOSC0`	`0x7e102090`	RW	24	`0x00ffffff`	`0x00820080`
`A2W_XOSC1`	`0x7e102094`	RW	24	`0x00ffffff`	`0x00000006`
`A2W_SMPS_CTLA0`	`0x7e1020a0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLA1`	`0x7e1020a4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLA2`	`0x7e1020a8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLB0`	`0x7e1020b0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLB1`	`0x7e1020b4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLB2`	`0x7e1020b8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC0`	`0x7e1020c0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC1`	`0x7e1020c4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC2`	`0x7e1020c8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC3`	`0x7e1020cc`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_LDO0`	`0x7e1020d0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_LDO1`	`0x7e1020d4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_DIG0`	`0x7e1020e0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_DIG1`	`0x7e1020e4`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLB_DIG2`	`0x7e1020e8`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLB_DIG3`	`0x7e1020ec`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLB_ANA0`	`0x7e1020f0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_ANA1`	`0x7e1020f4`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLB_ANA2`	`0x7e1020f8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_ANA3`	`0x7e1020fc`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLA_CTRL`	`0x7e102100`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLA_ANA_SSCS`	`0x7e102110`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLC_CTRL`	`0x7e102120`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLC_ANA_SSCS`	`0x7e102130`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLD_CTRL`	`0x7e102140`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLD_ANA_SSCS`	`0x7e102150`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLH_CTRL`	`0x7e102160`	RW	18	`0x000370ff`	`0x00010000`
`A2W_HDMI_CTL_RCAL`	`0x7e102180`	RW	17	`0x00011f33`	`0x00010000`
`A2W_XOSC_CTRL`	`0x7e102190`	RW	20	`0x000ff0ff`	`0000000000`
`A2W_SMPS_A_MODE`	`0x7e1021a0`	RW	1	`0x00000001`	`0000000000`
`A2W_SMPS_B_STAT`	`0x7e1021b0`	RW	13	`0x0000111f`	`0000000000`
`A2W_SMPS_C_CLK`	`0x7e1021c0`	RW	4	`0x0000000f`	`0000000000`
`A2W_SMPS_L_SPV`	`0x7e1021d0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLB_CTRL`	`0x7e1021e0`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLB_ANA_SSCS`	`0x7e1021f0`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLA_FRAC`	`0x7e102200`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLA_ANA_SSCL`	`0x7e102210`	RW	22	`0x003fffff`	`0000000000`
`A2W_PLLC_FRAC`	`0x7e102220`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLC_ANA_SSCL`	`0x7e102230`	RW	22	`0x003fffff`	`0000000000`
`A2W_PLLD_FRAC`	`0x7e102240`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLD_ANA_SSCL`	`0x7e102250`	RW	22	`0x003fffff`	`0000000000`
`A2W_PLLH_FRAC`	`0x7e102260`	RW	20	`0x000fffff`	`0000000000`
`A2W_HDMI_CTL_HFEN`	`0x7e102280`	RW	1	`0x00000001`	`0000000000`
`A2W_XOSC_CPR`	`0x7e102290`	RW	5	`0x00000013`	`0000000000`
`A2W_SMPS_A_VOLTS`	`0x7e1022a0`	RW	5	`0x0000001f`	`0000000000`
`A2W_SMPS_C_CTL`	`0x7e1022c0`	RW	2	`0x00000003`	`0000000000`
`A2W_SMPS_L_SPA`	`0x7e1022d0`	RW	10	`0x000003ff`	`0000000000`
`A2W_PLLB_FRAC`	`0x7e1022e0`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLB_ANA_SSCL`	`0x7e1022f0`	RW	22	`0x003fffff`	`0000000000`
`A2W_PLLA_DSI0`	`0x7e102300`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_KAIP`	`0x7e102310`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLC_CORE2`	`0x7e102320`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_KAIP`	`0x7e102330`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLD_DSI0`	`0x7e102340`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_KAIP`	`0x7e102350`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLH_AUX`	`0x7e102360`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLH_ANA_KAIP`	`0x7e102370`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_XOSC_BIAS`	`0x7e102390`	RW	5	`0x0000001f`	`0x00000018`
`A2W_SMPS_A_GAIN`	`0x7e1023a0`	RW	3	`0x00000007`	`0000000000`
`A2W_SMPS_L_SCV`	`0x7e1023d0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLB_ARM`	`0x7e1023e0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_KAIP`	`0x7e1023f0`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLA_CORE`	`0x7e102400`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_STAT`	`0x7e102410`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLC_CORE1`	`0x7e102420`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_STAT`	`0x7e102430`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLD_CORE`	`0x7e102440`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_STAT`	`0x7e102450`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLH_RCAL`	`0x7e102460`	RW	10	`0x000003ff`	`0x00000100`
`A2W_XOSC_PWR`	`0x7e102490`	RW	3	`0x00000007`	`0x00000004`
`A2W_SMPS_L_SCA`	`0x7e1024d0`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLB_SP0`	`0x7e1024e0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_STAT`	`0x7e1024f0`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLA_PER`	`0x7e102500`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_SCTL`	`0x7e102510`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLC_PER`	`0x7e102520`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_SCTL`	`0x7e102530`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLD_PER`	`0x7e102540`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_SCTL`	`0x7e102550`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLH_PIX`	`0x7e102560`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLH_ANA_SCTL`	`0x7e102570`	RW	5	`0x0000001f`	`0000000000`
`A2W_SMPS_L_SIV`	`0x7e1025d0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLB_SP1`	`0x7e1025e0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_SCTL`	`0x7e1025f0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLA_CCP2`	`0x7e102600`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_VCO`	`0x7e102610`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLC_CORE0`	`0x7e102620`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_VCO`	`0x7e102630`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLD_DSI1`	`0x7e102640`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_VCO`	`0x7e102650`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLH_ANA_STAT`	`0x7e102660`	RW	21	`0x001f1fff`	`0000000000`
`A2W_PLLH_ANA_VCO`	`0x7e102670`	RW	1	`0x00000001`	`0000000000`
`A2W_SMPS_L_SIA`	`0x7e1026d0`	RW	10	`0x000003ff`	`0000000000`
`A2W_PLLB_SP2`	`0x7e1026e0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_VCO`	`0x7e1026f0`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLA_DIG0R`	`0x7e102800`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLA_DIG1R`	`0x7e102804`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLA_DIG2R`	`0x7e102808`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLA_DIG3R`	`0x7e10280c`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLA_ANA0R`	`0x7e102810`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLA_ANA1R`	`0x7e102814`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLA_ANA2R`	`0x7e102818`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLA_ANA3R`	`0x7e10281c`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLC_DIG0R`	`0x7e102820`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLC_DIG1R`	`0x7e102824`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLC_DIG2R`	`0x7e102828`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLC_DIG3R`	`0x7e10282c`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLC_ANA0R`	`0x7e102830`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLC_ANA1R`	`0x7e102834`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLC_ANA2R`	`0x7e102838`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLC_ANA3R`	`0x7e10283c`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLD_DIG0R`	`0x7e102840`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLD_DIG1R`	`0x7e102844`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLD_DIG2R`	`0x7e102848`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLD_DIG3R`	`0x7e10284c`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLD_ANA0R`	`0x7e102850`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLD_ANA1R`	`0x7e102854`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLD_ANA2R`	`0x7e102858`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLD_ANA3R`	`0x7e10285c`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLH_DIG0R`	`0x7e102860`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_DIG1R`	`0x7e102864`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_DIG2R`	`0x7e102868`	RW	24	`0x00ffffff`	`0x000000aa`
`A2W_PLLH_DIG3R`	`0x7e10286c`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_ANA0R`	`0x7e102870`	RW	24	`0x00ffffff`	`0x00d80000`
`A2W_PLLH_ANA1R`	`0x7e102874`	RW	24	`0x00ffffff`	`0x00000014`
`A2W_PLLH_ANA2R`	`0x7e102878`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLH_ANA3R`	`0x7e10287c`	RW	24	`0x00ffffff`	`0000000000`
`A2W_HDMI_CTL0R`	`0x7e102880`	RW	24	`0x00ffffff`	`0x00470238`
`A2W_HDMI_CTL1R`	`0x7e102884`	RW	24	`0x00ffffff`	`0x00011c00`
`A2W_HDMI_CTL2R`	`0x7e102888`	RW	24	`0x00ffffff`	`0x0018048e`
`A2W_HDMI_CTL3R`	`0x7e10288c`	RW	24	`0x00ffffff`	`0x00000040`
`A2W_XOSC0R`	`0x7e102890`	RW	24	`0x00ffffff`	`0x00820080`
`A2W_XOSC1R`	`0x7e102894`	RW	24	`0x00ffffff`	`0x00000006`
`A2W_SMPS_CTLA0R`	`0x7e1028a0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLA1R`	`0x7e1028a4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLA2R`	`0x7e1028a8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLB0R`	`0x7e1028b0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLB1R`	`0x7e1028b4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLB2R`	`0x7e1028b8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC0R`	`0x7e1028c0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC1R`	`0x7e1028c4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC2R`	`0x7e1028c8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_CTLC3R`	`0x7e1028cc`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_LDO0R`	`0x7e1028d0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_SMPS_LDO1R`	`0x7e1028d4`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_DIG0R`	`0x7e1028e0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_DIG1R`	`0x7e1028e4`	RW	24	`0x00ffffff`	`0x00004000`
`A2W_PLLB_DIG2R`	`0x7e1028e8`	RW	24	`0x00ffffff`	`0x00100401`
`A2W_PLLB_DIG3R`	`0x7e1028ec`	RW	24	`0x00ffffff`	`0x00000004`
`A2W_PLLB_ANA0R`	`0x7e1028f0`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_ANA1R`	`0x7e1028f4`	RW	24	`0x00ffffff`	`0x001d0000`
`A2W_PLLB_ANA2R`	`0x7e1028f8`	RW	24	`0x00ffffff`	`0000000000`
`A2W_PLLB_ANA3R`	`0x7e1028fc`	RW	24	`0x00ffffff`	`0x00000180`
`A2W_PLLA_CTRLR`	`0x7e102900`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLA_ANA_SSCSR`	`0x7e102910`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLC_CTRLR`	`0x7e102920`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLC_ANA_SSCSR`	`0x7e102930`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLD_CTRLR`	`0x7e102940`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLD_ANA_SSCSR`	`0x7e102950`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLH_CTRLR`	`0x7e102960`	RW	18	`0x000370ff`	`0x00010000`
`A2W_HDMI_CTL_RCALR`	`0x7e102980`	RW	17	`0x00011f33`	`0x00010000`
`A2W_XOSC_CTRLR`	`0x7e102990`	RW	8	`0x000000ff`	`0000000000`
`A2W_SMPS_A_MODER`	`0x7e1029a0`	RW	1	`0x00000001`	`0000000000`
`A2W_SMPS_B_STATR`	`0x7e1029b0`	RW	13	`0x0000111f`	`0000000000`
`A2W_SMPS_C_CLKR`	`0x7e1029c0`	RW	4	`0x0000000f`	`0000000000`
`A2W_SMPS_L_SPVR`	`0x7e1029d0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLB_CTRLR`	`0x7e1029e0`	RW	18	`0x000373ff`	`0x00010000`
`A2W_PLLB_ANA_SSCSR`	`0x7e1029f0`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLA_FRACR`	`0x7e102a00`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLA_ANA_SSCLR`	`0x7e102a10`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLC_FRACR`	`0x7e102a20`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLC_ANA_SSCLR`	`0x7e102a30`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLD_FRACR`	`0x7e102a40`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLD_ANA_SSCLR`	`0x7e102a50`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLH_FRACR`	`0x7e102a60`	RW	20	`0x000fffff`	`0000000000`
`A2W_HDMI_CTL_HFENR`	`0x7e102a80`	RW	1	`0x00000001`	`0000000000`
`A2W_XOSC_CPRR`	`0x7e102a90`	RW	5	`0x00000013`	`0000000000`
`A2W_SMPS_A_VOLTSR`	`0x7e102aa0`	RW	5	`0x0000001f`	`0000000000`
`A2W_SMPS_C_CTLR`	`0x7e102ac0`	RW	2	`0x00000003`	`0000000000`
`A2W_SMPS_L_SPAR`	`0x7e102ad0`	RW	10	`0x000003ff`	`0000000000`
`A2W_PLLB_FRACR`	`0x7e102ae0`	RW	20	`0x000fffff`	`0000000000`
`A2W_PLLB_ANA_SSCLR`	`0x7e102af0`	RW	17	`0x0001ffff`	`0000000000`
`A2W_PLLA_DSI0R`	`0x7e102b00`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_KAIPR`	`0x7e102b10`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLC_CORE2R`	`0x7e102b20`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_KAIPR`	`0x7e102b30`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLD_DSI0R`	`0x7e102b40`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_KAIPR`	`0x7e102b50`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLH_AUXR`	`0x7e102b60`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLH_ANA_KAIPR`	`0x7e102b70`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_XOSC_BIASR`	`0x7e102b90`	RW	5	`0x0000001f`	`0x00000018`
`A2W_SMPS_A_GAINR`	`0x7e102ba0`	RW	3	`0x00000007`	`0000000000`
`A2W_SMPS_L_SCVR`	`0x7e102bd0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLB_ARMR`	`0x7e102be0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_KAIPR`	`0x7e102bf0`	RW	11	`0x0000077f`	`0x0000033a`
`A2W_PLLA_CORER`	`0x7e102c00`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_STATR`	`0x7e102c10`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLC_CORE1R`	`0x7e102c20`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_STATR`	`0x7e102c30`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLD_CORER`	`0x7e102c40`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_STATR`	`0x7e102c50`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLH_RCALR`	`0x7e102c60`	RW	10	`0x000003ff`	`0x00000100`
`A2W_XOSC_PWRR`	`0x7e102c90`	RW	3	`0x00000007`	`0x00000004`
`A2W_SMPS_L_SCAR`	`0x7e102cd0`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLB_SP0R`	`0x7e102ce0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_STATR`	`0x7e102cf0`	RW	12	`0x00000fff`	`0000000000`
`A2W_PLLA_PERR`	`0x7e102d00`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_SCTLR`	`0x7e102d10`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLC_PERR`	`0x7e102d20`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_SCTLR`	`0x7e102d30`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLD_PERR`	`0x7e102d40`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_SCTLR`	`0x7e102d50`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLH_PIXR`	`0x7e102d60`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLH_ANA_SCTLR`	`0x7e102d70`	RW	5	`0x0000001f`	`0000000000`
`A2W_SMPS_L_SIVR`	`0x7e102dd0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLB_SP1R`	`0x7e102de0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_SCTLR`	`0x7e102df0`	RW	5	`0x0000001f`	`0000000000`
`A2W_PLLA_CCP2R`	`0x7e102e00`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLA_ANA_VCOR`	`0x7e102e10`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLC_CORE0R`	`0x7e102e20`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLC_ANA_VCOR`	`0x7e102e30`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLD_DSI1R`	`0x7e102e40`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLD_ANA_VCOR`	`0x7e102e50`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLH_ANA_STATR`	`0x7e102e60`	RW	21	`0x001f1fff`	`0000000000`
`A2W_PLLH_ANA_VCOR`	`0x7e102e70`	RW	1	`0x00000001`	`0000000000`
`A2W_SMPS_L_SIAR`	`0x7e102ed0`	RW	10	`0x000003ff`	`0000000000`
`A2W_PLLB_SP2R`	`0x7e102ee0`	RW	10	`0x000003ff`	`0x00000100`
`A2W_PLLB_ANA_VCOR`	`0x7e102ef0`	RW	1	`0x00000001`	`0000000000`
`A2W_PLLA_MULTI`	`0x7e102f00`	RW	0	`0000000000`	`0000000000`
`A2W_PLLA_ANA_MULTI`	`0x7e102f10`	RW	0	`0000000000`	`0000000000`
`A2W_PLLC_MULTI`	`0x7e102f20`	RW	0	`0000000000`	`0000000000`
`A2W_PLLC_ANA_MULTI`	`0x7e102f30`	RW	0	`0000000000`	`0000000000`
`A2W_PLLD_MULTI`	`0x7e102f40`	RW	0	`0000000000`	`0000000000`
`A2W_PLLD_ANA_MULTI`	`0x7e102f50`	RW	0	`0000000000`	`0000000000`
`A2W_PLLH_MULTI`	`0x7e102f60`	RW	0	`0000000000`	`0000000000`
`A2W_PLLH_ANA_MULTI`	`0x7e102f70`	RW	0	`0000000000`	`0000000000`
`A2W_HDMI_CTL_MULTI`	`0x7e102f80`	RW	0	`0000000000`	`0000000000`
`A2W_XOSC_MULTI`	`0x7e102f90`	RW	0	`0000000000`	`0000000000`
`A2W_SMPS_A_MULTI`	`0x7e102fa0`	RW	0	`0000000000`	`0000000000`
`A2W_SMPS_B_MULTI`	`0x7e102fb0`	RW	0	`0000000000`	`0000000000`
`A2W_SMPS_C_MULTI`	`0x7e102fc0`	RW	0	`0000000000`	`0000000000`
`A2W_SMPS_L_MULTI`	`0x7e102fd0`	RW	0	`0000000000`	`0000000000`
`A2W_PLLB_MULTI`	`0x7e102fe0`	RW	0	`0000000000`	`0000000000`
`A2W_PLLB_ANA_MULTI`	`0x7e102ff0`	RW	0	`0000000000`	`0000000000`

Register details

A2W_PLLA_CTRL

Info

Name	value	description
address	`0x7e102100`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_CTRL_NDIV`	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
`missing definiton`	10	11	`NA`	`NA`	`NA`
`A2W_PLLA_CTRL_PDIV`	12	14	`0x00007000`	`0xffff8fff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`A2W_PLLA_CTRL_PWRDN`	16	16	`0x00010000`	`0xfffeffff`	`0x1`
`A2W_PLLA_CTRL_PRSTN`	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLA_ANA_SSCS

Info

Name	value	description
address	`0x7e102110`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLA_ANA_SSCS_STEP`	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
`A2W_PLLA_ANA_SSCS_MODE`	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLC_CTRL

Info

Name	value	description
address	`0x7e102120`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_CTRL_NDIV`	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
`missing definiton`	10	11	`NA`	`NA`	`NA`
`A2W_PLLC_CTRL_PDIV`	12	14	`0x00007000`	`0xffff8fff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`A2W_PLLC_CTRL_PWRDN`	16	16	`0x00010000`	`0xfffeffff`	`0x1`
`A2W_PLLC_CTRL_PRSTN`	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLC_ANA_SSCS

Info

Name	value	description
address	`0x7e102130`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLC_ANA_SSCS_STEP`	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
`A2W_PLLC_ANA_SSCS_MODE`	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLD_CTRL

Info

Name	value	description
address	`0x7e102140`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_CTRL_NDIV`	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
`missing definiton`	10	11	`NA`	`NA`	`NA`
`A2W_PLLD_CTRL_PDIV`	12	14	`0x00007000`	`0xffff8fff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`A2W_PLLD_CTRL_PWRDN`	16	16	`0x00010000`	`0xfffeffff`	`0x1`
`A2W_PLLD_CTRL_PRSTN`	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLD_ANA_SSCS

Info

Name	value	description
address	`0x7e102150`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLD_ANA_SSCS_STEP`	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
`A2W_PLLD_ANA_SSCS_MODE`	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLH_CTRL

Info

Name	value	description
address	`0x7e102160`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_CTRL_NDIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`missing definiton`	8	11	`NA`	`NA`	`NA`
`A2W_PLLH_CTRL_PDIV`	12	14	`0x00007000`	`0xffff8fff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`A2W_PLLH_CTRL_PWRDN`	16	16	`0x00010000`	`0xfffeffff`	`0x1`
`A2W_PLLH_CTRL_PRSTN`	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_HDMI_CTL_RCAL

Info

Name	value	description
address	`0x7e102180`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_HDMI_CTL_RCAL_SELAVG`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`A2W_HDMI_CTL_RCAL_SELDIV`	4	5	`0x00000030`	`0xffffffcf`	`0x0`
`missing definiton`	6	7	`NA`	`NA`	`NA`
`A2W_HDMI_CTL_RCAL_MANR`	8	11	`0x00000f00`	`0xfffff0ff`	`0x0`
`A2W_HDMI_CTL_RCAL_MANREN`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`missing definiton`	13	15	`NA`	`NA`	`NA`
`A2W_HDMI_CTL_RCAL_RSTB`	16	16	`0x00010000`	`0xfffeffff`	`0x1`

A2W_XOSC_CTRL

Info

Name	value	description
address	`0x7e102190`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_XOSC_CTRL_PLLCEN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`A2W_XOSC_CTRL_HDMIEN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`A2W_XOSC_CTRL_USBEN`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`A2W_XOSC_CTRL_SMPSEN`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`A2W_XOSC_CTRL_DDREN`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`A2W_XOSC_CTRL_PLLDEN`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`A2W_XOSC_CTRL_PLLAEN`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`A2W_XOSC_CTRL_PLLBEN`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`missing definiton`	8	11	`NA`	`NA`	`NA`
`A2W_XOSC_CTRL_PLLCOK`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`A2W_XOSC_CTRL_HDMIOK`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`A2W_XOSC_CTRL_USBOK`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`A2W_XOSC_CTRL_SMPSOK`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`A2W_XOSC_CTRL_DDROK`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`A2W_XOSC_CTRL_PLLDOK`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`A2W_XOSC_CTRL_PLLAOK`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`A2W_XOSC_CTRL_PLLBOK`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`

A2W_SMPS_A_MODE

Info

Name	value	description
address	`0x7e1021a0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_A_MODE_BSTPWMB`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_SMPS_B_STAT

Info

Name	value	description
address	`0x7e1021b0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_SMPS_B_STAT_VOLTS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`A2W_SMPS_B_STAT_BSTPWMB`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	11	`NA`	`NA`	`NA`
`A2W_SMPS_B_STAT_POK`	12	12	`0x00001000`	`0xffffefff`	`0x0`

A2W_SMPS_C_CLK

Info

Name	value	description
address	`0x7e1021c0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_SMPS_C_CLK_OSCDIV`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`A2W_SMPS_C_CLK_USEOSC`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`A2W_SMPS_C_CLK_TDEN`	3	3	`0x00000008`	`0xfffffff7`	`0x0`

A2W_SMPS_L_SPV

Info

Name	value	description
address	`0x7e1021d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_L_SPV_VOLTS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_PLLB_CTRL

Info

Name	value	description
address	`0x7e1021e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_CTRL_NDIV`	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
`missing definiton`	10	11	`NA`	`NA`	`NA`
`A2W_PLLB_CTRL_PDIV`	12	14	`0x00007000`	`0xffff8fff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`A2W_PLLB_CTRL_PWRDN`	16	16	`0x00010000`	`0xfffeffff`	`0x1`
`A2W_PLLB_CTRL_PRSTN`	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLB_ANA_SSCS

Info

Name	value	description
address	`0x7e1021f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLB_ANA_SSCS_STEP`	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
`A2W_PLLB_ANA_SSCS_MODE`	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLA_FRAC

Info

Name	value	description
address	`0x7e102200`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLA_FRAC_FRAC`	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLA_ANA_SSCL

Info

Name	value	description
address	`0x7e102210`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLA_ANA_SSCL_LIMIT`	0	21	`0x003fffff`	`0xffc00000`	`0x0`

A2W_PLLC_FRAC

Info

Name	value	description
address	`0x7e102220`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLC_FRAC_FRAC`	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLD_FRAC

Info

Name	value	description
address	`0x7e102240`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLD_FRAC_FRAC`	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLH_FRAC

Info

Name	value	description
address	`0x7e102260`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLH_FRAC_FRAC`	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_HDMI_CTL_HFEN

Info

Name	value	description
address	`0x7e102280`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_HDMI_CTL_HFEN_HFEN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_XOSC_CPR

Info

Name	value	description
address	`0x7e102290`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_XOSC_CPR_DIV`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`A2W_XOSC_CPR_CPR1`	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_SMPS_A_VOLTS

Info

Name	value	description
address	`0x7e1022a0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_A_VOLTS_VOLTS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_SMPS_C_CTL

Info

Name	value	description
address	`0x7e1022c0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_C_CTL_CTRLEN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`A2W_SMPS_C_CTL_UPEN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`

A2W_SMPS_L_SPA

Info

Name	value	description
address	`0x7e1022d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_L_SPA_ANA`	0	9	`0x000003ff`	`0xfffffc00`	`0x0`

A2W_PLLB_FRAC

Info

Name	value	description
address	`0x7e1022e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLB_FRAC_FRAC`	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLB_ANA_SSCL

Info

Name	value	description
address	`0x7e1022f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLB_ANA_SSCL_LIMIT`	0	21	`0x003fffff`	`0xffc00000`	`0x0`

A2W_PLLA_DSI0

Info

Name	value	description
address	`0x7e102300`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_DSI0_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLA_DSI0_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLA_DSI0_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_KAIP

Info

Name	value	description
address	`0x7e102310`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_ANA_KAIP_KP`	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
`A2W_PLLA_ANA_KAIP_KI`	4	6	`0x00000070`	`0xffffff8f`	`0x3`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`A2W_PLLA_ANA_KAIP_KA`	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLC_CORE2

Info

Name	value	description
address	`0x7e102320`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_CORE2_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLC_CORE2_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLC_CORE2_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_KAIP

Info

Name	value	description
address	`0x7e102330`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_ANA_KAIP_KP`	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
`A2W_PLLC_ANA_KAIP_KI`	4	6	`0x00000070`	`0xffffff8f`	`0x3`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`A2W_PLLC_ANA_KAIP_KA`	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLD_DSI0

Info

Name	value	description
address	`0x7e102340`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_DSI0_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLD_DSI0_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLD_DSI0_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_KAIP

Info

Name	value	description
address	`0x7e102350`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_ANA_KAIP_KP`	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
`A2W_PLLD_ANA_KAIP_KI`	4	6	`0x00000070`	`0xffffff8f`	`0x3`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`A2W_PLLD_ANA_KAIP_KA`	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLH_AUX

Info

Name	value	description
address	`0x7e102360`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_AUX_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLH_AUX_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLH_AUX_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLH_ANA_KAIP

Info

Name	value	description
address	`0x7e102370`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_ANA_KAIP_KP`	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
`A2W_PLLH_ANA_KAIP_KI`	4	6	`0x00000070`	`0xffffff8f`	`0x3`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`A2W_PLLH_ANA_KAIP_KA`	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_XOSC_BIAS

Info

Name	value	description
address	`0x7e102390`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_XOSC_BIAS_BIAS`	0	3	`0x0000000f`	`0xfffffff0`	`0x8`
`A2W_XOSC_BIAS_HIGHP`	4	4	`0x00000010`	`0xffffffef`	`0x1`

A2W_SMPS_A_GAIN

Info

Name	value	description
address	`0x7e1023a0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_A_GAIN_DIGGAIN`	0	2	`0x00000007`	`0xfffffff8`	`0x0`

A2W_SMPS_L_SCV

Info

Name	value	description
address	`0x7e1023d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_L_SCV_VOLTS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_PLLB_ARM

Info

Name	value	description
address	`0x7e1023e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_ARM_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLB_ARM_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLB_ARM_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_KAIP

Info

Name	value	description
address	`0x7e1023f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_ANA_KAIP_KP`	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
`A2W_PLLB_ANA_KAIP_KI`	4	6	`0x00000070`	`0xffffff8f`	`0x3`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`A2W_PLLB_ANA_KAIP_KA`	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLA_CORE

Info

Name	value	description
address	`0x7e102400`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_CORE_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLA_CORE_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLA_CORE_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_STAT

Info

Name	value	description
address	`0x7e102410`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLA_ANA_STAT_DATA`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLC_CORE1

Info

Name	value	description
address	`0x7e102420`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_CORE1_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLC_CORE1_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLC_CORE1_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_STAT

Info

Name	value	description
address	`0x7e102430`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLC_ANA_STAT_DATA`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLD_CORE

Info

Name	value	description
address	`0x7e102440`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_CORE_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLD_CORE_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLD_CORE_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_STAT

Info

Name	value	description
address	`0x7e102450`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLD_ANA_STAT_DATA`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLH_RCAL

Info

Name	value	description
address	`0x7e102460`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_RCAL_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLH_RCAL_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLH_RCAL_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_XOSC_PWR

Info

Name	value	description
address	`0x7e102490`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_XOSC_PWR_BYPASS`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`A2W_XOSC_PWR_PWRDN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`A2W_XOSC_PWR_RSTB`	2	2	`0x00000004`	`0xfffffffb`	`0x1`

A2W_SMPS_L_SCA

Info

Name	value	description
address	`0x7e1024d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_L_SCA_ANA`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLB_SP0

Info

Name	value	description
address	`0x7e1024e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_SP0_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLB_SP0_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLB_SP0_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_STAT

Info

Name	value	description
address	`0x7e1024f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLB_ANA_STAT_DATA`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLA_PER

Info

Name	value	description
address	`0x7e102500`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_PER_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLA_PER_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLA_PER_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_SCTL

Info

Name	value	description
address	`0x7e102510`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_ANA_SCTL_SEL`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`A2W_PLLA_ANA_SCTL_UPDATE`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`A2W_PLLA_ANA_SCTL_RESET`	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLC_PER

Info

Name	value	description
address	`0x7e102520`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_PER_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLC_PER_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLC_PER_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_SCTL

Info

Name	value	description
address	`0x7e102530`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_ANA_SCTL_SEL`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`A2W_PLLC_ANA_SCTL_UPDATE`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`A2W_PLLC_ANA_SCTL_RESET`	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLD_PER

Info

Name	value	description
address	`0x7e102540`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_PER_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLD_PER_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLD_PER_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_SCTL

Info

Name	value	description
address	`0x7e102550`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_ANA_SCTL_SEL`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`A2W_PLLD_ANA_SCTL_UPDATE`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`A2W_PLLD_ANA_SCTL_RESET`	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLH_PIX

Info

Name	value	description
address	`0x7e102560`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_PIX_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLH_PIX_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLH_PIX_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLH_ANA_SCTL

Info

Name	value	description
address	`0x7e102570`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_ANA_SCTL_SEL`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`A2W_PLLH_ANA_SCTL_UPDATE`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`A2W_PLLH_ANA_SCTL_RESET`	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_SMPS_L_SIV

Info

Name	value	description
address	`0x7e1025d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_L_SIV_VOLTS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_PLLB_SP1

Info

Name	value	description
address	`0x7e1025e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_SP1_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLB_SP1_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLB_SP1_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_SCTL

Info

Name	value	description
address	`0x7e1025f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_ANA_SCTL_SEL`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`A2W_PLLB_ANA_SCTL_UPDATE`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`A2W_PLLB_ANA_SCTL_RESET`	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLA_CCP2

Info

Name	value	description
address	`0x7e102600`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLA_CCP2_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLA_CCP2_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLA_CCP2_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_VCO

Info

Name	value	description
address	`0x7e102610`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLA_ANA_VCO_RANGE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_PLLC_CORE0

Info

Name	value	description
address	`0x7e102620`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLC_CORE0_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLC_CORE0_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLC_CORE0_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_VCO

Info

Name	value	description
address	`0x7e102630`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLC_ANA_VCO_RANGE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_PLLD_DSI1

Info

Name	value	description
address	`0x7e102640`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLD_DSI1_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLD_DSI1_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLD_DSI1_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_VCO

Info

Name	value	description
address	`0x7e102650`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLD_ANA_VCO_RANGE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_PLLH_ANA_STAT

Info

Name	value	description
address	`0x7e102660`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLH_ANA_STAT_DATA`	0	11	`0x00000fff`	`0xfffff000`	`0x0`
`A2W_PLLH_ANA_STAT_RCALDONE`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`missing definiton`	13	15	`NA`	`NA`	`NA`
`A2W_PLLH_ANA_STAT_RCALCODE`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`A2W_PLLH_ANA_STAT_CNTLENB`	20	20	`0x00100000`	`0xffefffff`	`0x0`

A2W_PLLH_ANA_VCO

Info

Name	value	description
address	`0x7e102670`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLH_ANA_VCO_RANGE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_SMPS_L_SIA

Info

Name	value	description
address	`0x7e1026d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_SMPS_L_SIA_ANA`	0	9	`0x000003ff`	`0xfffffc00`	`0x0`

A2W_PLLB_SP2

Info

Name	value	description
address	`0x7e1026e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`A2W_PLLB_SP2_DIV`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`A2W_PLLB_SP2_CHENB`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`A2W_PLLB_SP2_BYPEN`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_VCO

Info

Name	value	description
address	`0x7e1026f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`A2W_PLLB_ANA_VCO_RANGE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

APERF0

Description

TODO

Info

Name	value	description
base	`0x7e009800`
id	`0x41584950`

Registers

name	address	type	width	mask	reset
`APERF0_GEN_CTRL`	`0x7e009800`	RW	2	`0x00000003`	`0000000000`
`APERF0_BW0_CTRL`	`0x7e009840`	RW	32	`0xf0001f1f`	`0000000000`
`APERF0_BW0_ATRANS`	`0x7e009844`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW0_ATWAIT`	`0x7e009848`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW0_AMAX`	`0x7e00984c`	RO	24	`0x00ffffff`	`0000000000`
`APERF0_BW0_WTRANS`	`0x7e009850`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW0_WTWAIT`	`0x7e009854`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW0_WMAX`	`0x7e009858`	RO	24	`0x00ffffff`	`0000000000`
`APERF0_BW0_RTRANS`	`0x7e00985c`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW0_RTWAIT`	`0x7e009860`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW0_RMAX`	`0x7e009864`	RO	24	`0x00ffffff`	`0000000000`
`APERF0_BW0_RPEND`	`0x7e009868`	RO	8	`0x000000ff`	`0000000000`
`APERF0_BW2_RPEND`	`0x7e009868`	RO	8	`0x000000ff`	`0000000000`
`APERF0_BW1_RPEND`	`0x7e009868`	RO	8	`0x000000ff`	`0000000000`
`APERF0_BW1_CTRL`	`0x7e009880`	RW	32	`0xf0001f1f`	`0000000000`
`APERF0_BW1_ATRANS`	`0x7e009884`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW1_ATWAIT`	`0x7e009888`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW1_AMAX`	`0x7e00988c`	RO	24	`0x00ffffff`	`0000000000`
`APERF0_BW1_WTRANS`	`0x7e009890`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW1_WTWAIT`	`0x7e009894`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW1_WMAX`	`0x7e009898`	RO	16	`0x0000ffff`	`0000000000`
`APERF0_BW1_RTRANS`	`0x7e00989c`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW1_RTWAIT`	`0x7e0098a0`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW1_RMAX`	`0x7e0098a4`	RO	24	`0x00ffffff`	`0000000000`
`APERF0_BW2_CTRL`	`0x7e0098c0`	RW	32	`0xf0001f1f`	`0000000000`
`APERF0_BW2_ATRANS`	`0x7e0098c4`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW2_ATWAIT`	`0x7e0098c8`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW2_AMAX`	`0x7e0098cc`	RO	24	`0x00ffffff`	`0000000000`
`APERF0_BW2_WTRANS`	`0x7e0098d0`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW2_WTWAIT`	`0x7e0098d4`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW2_WMAX`	`0x7e0098d8`	RO	28	`0x0ff0ffff`	`0000000000`
`APERF0_BW2_RTRANS`	`0x7e0098dc`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW2_RTWAIT`	`0x7e0098e0`	RO	32	`0xffffffff`	`0000000000`
`APERF0_BW2_RMAX`	`0x7e0098e4`	RO	24	`0x00ffffff`	`0000000000`

Register details

APERF0_GEN_CTRL

Info

Name	value	description
address	`0x7e009800`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`APERF0_GEN_CTRL_ENABLE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`APERF0_GEN_CTRL_RESET`	1	1	`0x00000002`	`0xfffffffd`	`0x0`

APERF0_BW0_CTRL

Info

Name	value	description
address	`0x7e009840`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`APERF0_BW0_CTRL_BUS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`APERF0_BW0_CTRL_ID`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	27	`NA`	`NA`	`NA`
`APERF0_BW0_CTRL_LATHALT`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`APERF0_BW0_CTRL_ID_EN`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`APERF0_BW0_CTRL_EN`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`APERF0_BW0_CTRL_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

APERF0_BW1_CTRL

Info

Name	value	description
address	`0x7e009880`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`APERF0_BW1_CTRL_BUS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`APERF0_BW1_CTRL_ID`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	27	`NA`	`NA`	`NA`
`APERF0_BW1_CTRL_LATHALT`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`APERF0_BW1_CTRL_ID_EN`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`APERF0_BW1_CTRL_EN`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`APERF0_BW1_CTRL_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

APERF0_BW2_CTRL

Info

Name	value	description
address	`0x7e0098c0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`APERF0_BW2_CTRL_BUS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`APERF0_BW2_CTRL_ID`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	27	`NA`	`NA`	`NA`
`APERF0_BW2_CTRL_LATHALT`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`APERF0_BW2_CTRL_ID_EN`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`APERF0_BW2_CTRL_EN`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`APERF0_BW2_CTRL_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

APERF1

Description

TODO

Info

Name	value	description
base	`0x7ee08000`
id	`0x41584950`

Registers

name	address	type	width	mask	reset
`APERF1_GEN_CTRL`	`0x7ee08000`	RW	2	`0x00000003`	`0000000000`
`APERF1_BW0_CTRL`	`0x7ee08040`	RW	32	`0xf0001f1f`	`0000000000`
`APERF1_BW0_ATRANS`	`0x7ee08044`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW0_ATWAIT`	`0x7ee08048`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW0_AMAX`	`0x7ee0804c`	RO	24	`0x00ffffff`	`0000000000`
`APERF1_BW0_WTRANS`	`0x7ee08050`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW0_WTWAIT`	`0x7ee08054`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW0_WMAX`	`0x7ee08058`	RO	24	`0x00ffffff`	`0000000000`
`APERF1_BW0_RTRANS`	`0x7ee0805c`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW0_RTWAIT`	`0x7ee08060`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW0_RMAX`	`0x7ee08064`	RO	24	`0x00ffffff`	`0000000000`
`APERF1_BW0_RPEND`	`0x7ee08068`	RO	8	`0x000000ff`	`0000000000`
`APERF1_BW1_RPEND`	`0x7ee08068`	RO	8	`0x000000ff`	`0000000000`
`APERF1_BW2_RPEND`	`0x7ee08068`	RO	8	`0x000000ff`	`0000000000`
`APERF1_BW1_CTRL`	`0x7ee08080`	RW	32	`0xf0001f1f`	`0000000000`
`APERF1_BW1_ATRANS`	`0x7ee08084`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW1_ATWAIT`	`0x7ee08088`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW1_AMAX`	`0x7ee0808c`	RO	24	`0x00ffffff`	`0000000000`
`APERF1_BW1_WTRANS`	`0x7ee08090`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW1_WTWAIT`	`0x7ee08094`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW1_WMAX`	`0x7ee08098`	RO	16	`0x0000ffff`	`0000000000`
`APERF1_BW1_RTRANS`	`0x7ee0809c`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW1_RTWAIT`	`0x7ee080a0`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW1_RMAX`	`0x7ee080a4`	RO	24	`0x00ffffff`	`0000000000`
`APERF1_BW2_CTRL`	`0x7ee080c0`	RW	32	`0xf0001f1f`	`0000000000`
`APERF1_BW2_ATRANS`	`0x7ee080c4`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW2_ATWAIT`	`0x7ee080c8`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW2_AMAX`	`0x7ee080cc`	RO	24	`0x00ffffff`	`0000000000`
`APERF1_BW2_WTRANS`	`0x7ee080d0`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW2_WTWAIT`	`0x7ee080d4`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW2_WMAX`	`0x7ee080d8`	RO	28	`0x0ff0ffff`	`0000000000`
`APERF1_BW2_RTRANS`	`0x7ee080dc`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW2_RTWAIT`	`0x7ee080e0`	RO	32	`0xffffffff`	`0000000000`
`APERF1_BW2_RMAX`	`0x7ee080e4`	RO	24	`0x00ffffff`	`0000000000`

Register details

APERF1_GEN_CTRL

Info

Name	value	description
address	`0x7ee08000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`APERF1_GEN_CTRL_ENABLE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`APERF1_GEN_CTRL_RESET`	1	1	`0x00000002`	`0xfffffffd`	`0x0`

APERF1_BW0_CTRL

Info

Name	value	description
address	`0x7ee08040`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`APERF1_BW0_CTRL_BUS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`APERF1_BW0_CTRL_ID`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	27	`NA`	`NA`	`NA`
`APERF1_BW0_CTRL_LATHALT`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`APERF1_BW0_CTRL_ID_EN`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`APERF1_BW0_CTRL_EN`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`APERF1_BW0_CTRL_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

APERF1_BW1_CTRL

Info

Name	value	description
address	`0x7ee08080`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`APERF1_BW1_CTRL_BUS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`APERF1_BW1_CTRL_ID`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	27	`NA`	`NA`	`NA`
`APERF1_BW1_CTRL_LATHALT`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`APERF1_BW1_CTRL_ID_EN`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`APERF1_BW1_CTRL_EN`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`APERF1_BW1_CTRL_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

APERF1_BW2_CTRL

Info

Name	value	description
address	`0x7ee080c0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`APERF1_BW2_CTRL_BUS`	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`APERF1_BW2_CTRL_ID`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	27	`NA`	`NA`	`NA`
`APERF1_BW2_CTRL_LATHALT`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`APERF1_BW2_CTRL_ID_EN`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`APERF1_BW2_CTRL_EN`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`APERF1_BW2_CTRL_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

APHY_CSR

Description

TODO

Info

Name	value	description
base	`0x7ee06000`

Registers

name	address	type
`APHY_CSR_ADDR_REV_ID`	`0x7ee06000`	RW
`APHY_CSR_GLBL_ADDR_DLL_RESET`	`0x7ee06004`	RW
`APHY_CSR_GLBL_ADDR_DLL_RECAL`	`0x7ee06008`	RW
`APHY_CSR_GLBL_ADDR_DLL_CNTRL`	`0x7ee0600c`	RW
`APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL`	`0x7ee06010`	RW
`APHY_CSR_ADDR_MASTER_DLL_OUTPUT`	`0x7ee06014`	RW
`APHY_CSR_ADDR_SLAVE_DLL_OFFSET`	`0x7ee06018`	RW
`APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN`	`0x7ee0601c`	RW
`APHY_CSR_GLBL_ADR_DLL_LOCK_STAT`	`0x7ee06020`	RW
`APHY_CSR_DDR_PLL_GLOBAL_RESET`	`0x7ee06024`	RW
`APHY_CSR_DDR_PLL_POST_DIV_RESET`	`0x7ee06028`	RW
`APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0`	`0x7ee0602c`	RW
`APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1`	`0x7ee06030`	RW
`APHY_CSR_DDR_PLL_MDIV_VALUE`	`0x7ee06034`	RW
`APHY_CSR_DDR_PLL_CONFIG_CNTRL`	`0x7ee06038`	RW
`APHY_CSR_DDR_PLL_MISC_CNTRL`	`0x7ee0603c`	RW
`APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0`	`0x7ee06040`	RW
`APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1`	`0x7ee06044`	RW
`APHY_CSR_DDR_PLL_LOCK_STATUS`	`0x7ee06048`	RW
`APHY_CSR_DDR_PLL_HOLD_CH`	`0x7ee0604c`	RW
`APHY_CSR_DDR_PLL_ENABLE_CH`	`0x7ee06050`	RW
`APHY_CSR_DDR_PLL_BYPASS`	`0x7ee06054`	RW
`APHY_CSR_DDR_PLL_PWRDWN`	`0x7ee06058`	RW
`APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL`	`0x7ee0605c`	RW
`APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL`	`0x7ee06060`	RW
`APHY_CSR_DDR_PLL_DESKEW_STATUS`	`0x7ee06064`	RW
`APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL`	`0x7ee06068`	RW
`APHY_CSR_ADDR_PAD_MISC_CTRL`	`0x7ee0606c`	RW
`APHY_CSR_ADDR_PVT_COMP_CTRL`	`0x7ee06070`	RW
`APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL`	`0x7ee06074`	RW
`APHY_CSR_ADDR_PVT_COMP_STATUS`	`0x7ee06078`	RW
`APHY_CSR_ADDR_PVT_COMP_DEBUG`	`0x7ee0607c`	RW
`APHY_CSR_PHY_BIST_CNTRL_SPR`	`0x7ee06080`	RW
`APHY_CSR_PHY_BIST_CA_CRC_SPR`	`0x7ee06084`	RW
`APHY_CSR_ADDR_SPR0_RW`	`0x7ee06088`	RW
`APHY_CSR_ADDR_SPR1_RO`	`0x7ee0608c`	RW
`APHY_CSR_ADDR_SPR_RO`	`0x7ee06090`	RW

Register details

ASB

Description

TODO

Info

Name	value	description
base	`0x7e00a000`
id	`0x62726467`

Registers

name	address	type	width	mask	reset
`ASB_AXI_BRDG_VERSION`	`0x7e00a000`	RW	8	`0x000000ff`	`0000000000`
`ASB_CPR_CTRL`	`0x7e00a004`	RW	24	`0x00ffffff`	`0x00000007`
`ASB_V3D_S_CTRL`	`0x7e00a008`	RW	24	`0x00ffffff`	`0x00000007`
`ASB_V3D_M_CTRL`	`0x7e00a00c`	RW	24	`0x00ffffff`	`0x00000007`
`ASB_ISP_S_CTRL`	`0x7e00a010`	RW	24	`0x00ffffff`	`0x00000007`
`ASB_ISP_M_CTRL`	`0x7e00a014`	RW	24	`0x00ffffff`	`0x00000007`
`ASB_H264_S_CTRL`	`0x7e00a018`	RW	24	`0x00ffffff`	`0x00000007`
`ASB_H264_M_CTRL`	`0x7e00a01c`	RW	24	`0x00ffffff`	`0x00000007`

Register details

ASB_CPR_CTRL

Info

Name	value	description
address	`0x7e00a004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_CPR_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_CPR_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_CPR_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_CPR_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_CPR_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_CPR_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

ASB_V3D_S_CTRL

Info

Name	value	description
address	`0x7e00a008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_V3D_S_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_V3D_S_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_V3D_S_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_V3D_S_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_V3D_S_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_V3D_S_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

ASB_V3D_M_CTRL

Info

Name	value	description
address	`0x7e00a00c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_V3D_M_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_V3D_M_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_V3D_M_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_V3D_M_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_V3D_M_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_V3D_M_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

ASB_ISP_S_CTRL

Info

Name	value	description
address	`0x7e00a010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_ISP_S_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_ISP_S_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_ISP_S_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_ISP_S_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_ISP_S_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_ISP_S_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

ASB_ISP_M_CTRL

Info

Name	value	description
address	`0x7e00a014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_ISP_M_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_ISP_M_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_ISP_M_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_ISP_M_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_ISP_M_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_ISP_M_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

ASB_H264_S_CTRL

Info

Name	value	description
address	`0x7e00a018`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_H264_S_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_H264_S_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_H264_S_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_H264_S_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_H264_S_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_H264_S_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

ASB_H264_M_CTRL

Info

Name	value	description
address	`0x7e00a01c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`ASB_H264_M_CTRL_CLR_REQ`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`ASB_H264_M_CTRL_CLR_ACK`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`ASB_H264_M_CTRL_EMPTY`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`ASB_H264_M_CTRL_FULL`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`ASB_H264_M_CTRL_RCOUNT`	4	13	`0x00003ff0`	`0xffffc00f`	`0x0`
`ASB_H264_M_CTRL_WCOUNT`	14	23	`0x00ffc000`	`0xff003fff`	`0x0`

AVE_IN

Description

TODO

Info

Name	value	description
base	`0x7e910000`
id	`0x61766530`

Registers

name	address	type	width	mask	reset
`AVE_IN_CTRL`	`0x7e910000`	RW	32	`0x87ffffff`	`0x08000080`
`AVE_IN_STATUS`	`0x7e910004`	RW	32	`0x9f733f7f`	`0000000000`
`AVE_IN_BUF0_ADDRESS`	`0x7e910008`	RW	32	`0xffffffff`	`0000000000`
`AVE_IN_BUF1_ADDRESS`	`0x7e91000c`	RW	32	`0xffffffff`	`0000000000`
`AVE_IN_MAX_TRANSFER`	`0x7e910010`	RW	32	`0xffffffff`	`0000000000`
`AVE_IN_LINE_LENGTH`	`0x7e910014`	RW	12	`0x00000fff`	`0000000000`
`AVE_IN_CURRENT_ADDRESS`	`0x7e910018`	RW	32	`0xffffffff`	`0000000000`
`AVE_IN_CURRENT_LINE_BUF0`	`0x7e91001c`	RW	32	`0x80000fff`	`0000000000`
`AVE_IN_CURRENT_LINE_BUF1`	`0x7e910020`	RW	32	`0x80000fff`	`0000000000`
`AVE_IN_CURRENT_LINE_NUM`	`0x7e910024`	RW	32	`0xe0000fff`	`0000000000`
`AVE_IN_OVERRUN_ADDRESS`	`0x7e910028`	RW	32	`0xffffffff`	`0000000000`
`AVE_IN_LINE_NUM_INT`	`0x7e91002c`	RW	12	`0x00000fff`	`0000000000`
`AVE_IN_CALC_LINE_STEP`	`0x7e910030`	RW	12	`0x00000fff`	`0000000000`
`AVE_IN_OUTSTANDING_BUFF0`	`0x7e910034`	RW	8	`0x000000ff`	`0000000000`
`AVE_IN_OUTSTANDING_BUFF1`	`0x7e910038`	RW	8	`0x000000ff`	`0000000000`
`AVE_IN_CHAR_CTRL`	`0x7e91003c`	RW	32	`0x8000000f`	`0000000000`
`AVE_IN_SYNC_CTRL`	`0x7e910040`	RW	8	`0x0000008f`	`0000000000`
`AVE_IN_FRAME_NUM`	`0x7e910044`	RW	12	`0x00000fff`	`0000000000`
`AVE_IN_BLOCK_ID`	`0x7e910060`	RW	32	`0xffffffff`	`0x61766530`

Register details

AVE_IN_CTRL

Info

Name	value	description
address	`0x7e910000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_IN_CTRL_OVERRUN_IRQ_EN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`AVE_IN_CTRL_BUF0_IRQ_EN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`AVE_IN_CTRL_BUF1_IRQ_EN`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`AVE_IN_CTRL_BUF_SER_IRQ_EN`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`AVE_IN_CTRL_LINE_IRQ_EN`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`AVE_IN_CTRL_HSYNC_IRQ_EN`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`AVE_IN_CTRL_FRAME_RATE_IRQ_EN`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`AVE_IN_CTRL_PRIV_MODE`	7	7	`0x00000080`	`0xffffff7f`	`0x1`
`AVE_IN_CTRL_LENGTH_IN_PXLS`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`AVE_IN_CTRL_FRAME_MODE`	9	10	`0x00000600`	`0xfffff9ff`	`0x0`
`AVE_IN_CTRL_BYTE_ORDER`	11	13	`0x00003800`	`0xffffc7ff`	`0x0`
`AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`AVE_IN_CTRL_EN_OVERRUN_ABORT`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`AVE_IN_CTRL_LOW_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`AVE_IN_CTRL_HIGH_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`AVE_IN_CTRL_PRIORITY_LIMIT`	24	26	`0x07000000`	`0xf8ffffff`	`0x0`
`missing definiton`	27	30	`NA`	`NA`	`NA`
`AVE_IN_CTRL_ENABLE`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

AVE_IN_STATUS

Info

Name	value	description
address	`0x7e910004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_IN_STATUS_OVERRUN_DET`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`AVE_IN_STATUS_BUF0_COMPL`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`AVE_IN_STATUS_BUF1_COMPL`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`AVE_IN_STATUS_BUF_NOT_SERV`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`AVE_IN_STATUS_LINE_NUM_HIT`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`AVE_IN_STATUS_HSYNC_DET`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`AVE_IN_STATUS_FRAME_RATE_DET`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`AVE_IN_STATUS_FRAME_RATE`	8	9	`0x00000300`	`0xfffffcff`	`0x0`
`AVE_IN_STATUS_INTERLACED`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`AVE_IN_STATUS_EVEN_FIELD`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`AVE_IN_STATUS_VFORM_FIELD`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`AVE_IN_STATUS_CSYNC_FIELD`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`missing definiton`	14	15	`NA`	`NA`	`NA`
`AVE_IN_STATUS_MAX_HIT`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`AVE_IN_STATUS_CURRENT_BUF`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`missing definiton`	18	19	`NA`	`NA`	`NA`
`AVE_IN_STATUS_AXI_STATE`	20	22	`0x00700000`	`0xff8fffff`	`0x0`
`missing definiton`	23	23	`NA`	`NA`	`NA`
`AVE_IN_STATUS_OVERRUN_CNT`	24	28	`0x1f000000`	`0xe0ffffff`	`0x0`
`missing definiton`	29	30	`NA`	`NA`	`NA`
`AVE_IN_STATUS_CAPTURING`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

AVE_IN_BUF0_ADDRESS

Info

Name	value	description
address	`0x7e910008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_BUF0_ADDRESS_BUF0_ADDR`	0	31	`0xffffffff`	`0x00000000`	`0x0`

AVE_IN_BUF1_ADDRESS

Info

Name	value	description
address	`0x7e91000c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_BUF1_ADDRESS_BUF1_ADDR`	0	31	`0xffffffff`	`0x00000000`	`0x0`

AVE_IN_MAX_TRANSFER

Info

Name	value	description
address	`0x7e910010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_MAX_TRANSFER_MAX_TRANSFER`	0	31	`0xffffffff`	`0x00000000`	`0x0`

AVE_IN_LINE_LENGTH

Info

Name	value	description
address	`0x7e910014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_LINE_LENGTH_LINE_LENGTH`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

AVE_IN_CURRENT_ADDRESS

Info

Name	value	description
address	`0x7e910018`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_CURRENT_ADDRESS_CUR_ADDR`	0	31	`0xffffffff`	`0x00000000`	`0x0`

AVE_IN_CURRENT_LINE_BUF0

Info

Name	value	description
address	`0x7e91001c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE`	0	11	`0x00000fff`	`0xfffff000`	`0x0`
`missing definiton`	12	30	`NA`	`NA`	`NA`
`AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

AVE_IN_CURRENT_LINE_BUF1

Info

Name	value	description
address	`0x7e910020`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE`	0	11	`0x00000fff`	`0xfffff000`	`0x0`
`missing definiton`	12	30	`NA`	`NA`	`NA`
`AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

AVE_IN_CURRENT_LINE_NUM

Info

Name	value	description
address	`0x7e910024`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE`	0	11	`0x00000fff`	`0xfffff000`	`0x0`
`missing definiton`	12	28	`NA`	`NA`	`NA`
`AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`AVE_IN_CURRENT_LINE_NUM_INTERLACED`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

AVE_IN_OVERRUN_ADDRESS

Info

Name	value	description
address	`0x7e910028`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR`	0	31	`0xffffffff`	`0x00000000`	`0x0`

AVE_IN_LINE_NUM_INT

Info

Name	value	description
address	`0x7e91002c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_LINE_NUM_INT_LINE_NUM_INT`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

AVE_IN_CALC_LINE_STEP

Info

Name	value	description
address	`0x7e910030`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

AVE_IN_FRAME_NUM

Info

Name	value	description
address	`0x7e910044`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`AVE_IN_FRAME_NUM_FRAME_NUM`	0	11	`0x00000fff`	`0xfffff000`	`0x0`

AVE_OUT

Description

TODO

Info

Name	value	description
base	`0x7e240000`
id	`0x61766538`

Registers

name	address	type	width	mask	reset
`AVE_OUT_CTRL`	`0x7e240000`	RW	32	`0xc0fff13f`	`0x40000100`
`AVE_OUT_STATUS`	`0x7e240004`	RW	10	`0x000003f7`	`0000000000`
`AVE_OUT_OFFSET`	`0x7e240008`	RW	32	`0x80ffffff`	`0x80109090`
`AVE_OUT_Y_COEFF`	`0x7e24000c`	RW	30	`0x3fffffff`	`0x0994b43a`
`AVE_OUT_CB_COEFF`	`0x7e240010`	RW	30	`0x3fffffff`	`0x3a9d5900`
`AVE_OUT_CR_COEFF`	`0x7e240014`	RW	30	`0x3fffffff`	`0x100ca7d6`
`AVE_OUT_BLOCK_ID`	`0x7e240060`	RW	32	`0xffffffff`	`0x61766538`

Register details

AVE_OUT_CTRL

Info

Name	value	description
address	`0x7e240000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_OUT_CTRL_ERROR_IRQ_EN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`AVE_OUT_CTRL_COEFF_IRQ_EN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`AVE_OUT_CTRL_REFRESH_RATE`	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
`AVE_OUT_CTRL_MODE`	4	5	`0x00000030`	`0xffffffcf`	`0x0`
`missing definiton`	6	7	`NA`	`NA`	`NA`
`AVE_OUT_CTRL_PRIV_ACCESS`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`missing definiton`	9	11	`NA`	`NA`	`NA`
`AVE_OUT_CTRL_INTERLEAVE`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`AVE_OUT_CTRL_NTSC_PAL_IDENT`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`AVE_OUT_CTRL_INVERT_HSYNC`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`AVE_OUT_CTRL_INVERT_VSYNC`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`AVE_OUT_CTRL_INVERT_EVEN_FIELD`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`AVE_OUT_CTRL_INVERT_CSYNC`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`AVE_OUT_CTRL_INVERT_DSYNC`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`AVE_OUT_CTRL_BYTE_SWAP`	19	23	`0x00f80000`	`0xff07ffff`	`0x0`
`missing definiton`	24	29	`NA`	`NA`	`NA`
`AVE_OUT_CTRL_SOFT_RESET`	30	30	`0x40000000`	`0xbfffffff`	`0x1`
`AVE_OUT_CTRL_ENABLE`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

AVE_OUT_STATUS

Info

Name	value	description
address	`0x7e240004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_OUT_STATUS_PXL_FORMAT_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`AVE_OUT_STATUS_PXL_OUTPUT_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`AVE_OUT_STATUS_COEFF_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`AVE_OUT_STATUS_HFRONT_PORCH`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`AVE_OUT_STATUS_HBACK_PORCH`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`AVE_OUT_STATUS_HSYNC`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`AVE_OUT_STATUS_VFRONT_PORCH`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`AVE_OUT_STATUS_VBACK_PORCH`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`AVE_OUT_STATUS_VSYNC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

AVE_OUT_OFFSET

Info

Name	value	description
address	`0x7e240008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_OUT_OFFSET_BLUE_OFFSET`	0	7	`0x000000ff`	`0xffffff00`	`0x90`
`AVE_OUT_OFFSET_GREEN_OFFSET`	8	15	`0x0000ff00`	`0xffff00ff`	`0x90`
`AVE_OUT_OFFSET_RED_OFFSET`	16	23	`0x00ff0000`	`0xff00ffff`	`0x10`
`missing definiton`	24	30	`NA`	`NA`	`NA`
`AVE_OUT_OFFSET_EN_YCBCR_CLAMPING`	31	31	`0x80000000`	`0x7fffffff`	`0x1`

AVE_OUT_Y_COEFF

Info

Name	value	description
address	`0x7e24000c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_OUT_Y_COEFF_BLUE_COEFF`	0	9	`0x000003ff`	`0xfffffc00`	`0x3a`
`AVE_OUT_Y_COEFF_GREEN_COEFF`	10	19	`0x000ffc00`	`0xfff003ff`	`0x12d`
`AVE_OUT_Y_COEFF_RED_COEFF`	20	29	`0x3ff00000`	`0xc00fffff`	`0x99`

AVE_OUT_CB_COEFF

Info

Name	value	description
address	`0x7e240010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_OUT_CB_COEFF_BLUE_COEFF`	0	9	`0x000003ff`	`0xfffffc00`	`0x100`
`AVE_OUT_CB_COEFF_GREEN_COEFF`	10	19	`0x000ffc00`	`0xfff003ff`	`0x356`
`AVE_OUT_CB_COEFF_RED_COEFF`	20	29	`0x3ff00000`	`0xc00fffff`	`0x3a9`

AVE_OUT_CR_COEFF

Info

Name	value	description
address	`0x7e240014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`AVE_OUT_CR_COEFF_BLUE_COEFF`	0	9	`0x000003ff`	`0xfffffc00`	`0x3d6`
`AVE_OUT_CR_COEFF_GREEN_COEFF`	10	19	`0x000ffc00`	`0xfff003ff`	`0x329`
`AVE_OUT_CR_COEFF_RED_COEFF`	20	29	`0x3ff00000`	`0xc00fffff`	`0x100`

CAM0

Description

TODO

Info

Name	value	description
base	`0x7e800000`
id	`0x7563616d`

Registers

name	address	type	width	mask	reset
`CAM0_CAMCTL`	`0x7e800000`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMSTA`	`0x7e800004`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMANA`	`0x7e800008`	RW	32	`0xffffffff`	`0x00000777`
`CAM0_CAMPRI`	`0x7e80000c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMCLK`	`0x7e800010`	RW	32	`0xffffffff`	`0x00000002`
`CAM0_CAMCLT`	`0x7e800014`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDAT0`	`0x7e800018`	RW	32	`0xffffffff`	`0x00000002`
`CAM0_CAMDAT1`	`0x7e80001c`	RW	32	`0xffffffff`	`0x00000002`
`CAM0_CAMDAT2`	`0x7e800020`	RW	32	`0xffffffff`	`0x00000002`
`CAM0_CAMDAT3`	`0x7e800024`	RW	32	`0xffffffff`	`0x00000002`
`CAM0_CAMDLT`	`0x7e800028`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMCMP0`	`0x7e80002c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMCMP1`	`0x7e800030`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMCAP0`	`0x7e800034`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMCAP1`	`0x7e800038`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBG0`	`0x7e8000f0`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBG1`	`0x7e8000f4`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBG2`	`0x7e8000f8`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBG3`	`0x7e8000fc`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMICTL`	`0x7e800100`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMISTA`	`0x7e800104`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDI0`	`0x7e800108`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIPIPE`	`0x7e80010c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIBSA0`	`0x7e800110`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIBEA0`	`0x7e800114`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIBLS`	`0x7e800118`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIBWP`	`0x7e80011c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIHWIN`	`0x7e800120`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIHSTA`	`0x7e800124`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIVWIN`	`0x7e800128`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIVSTA`	`0x7e80012c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMICC`	`0x7e800130`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMICS`	`0x7e800134`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDC`	`0x7e800138`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDPO`	`0x7e80013c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDCA`	`0x7e800140`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDCD`	`0x7e800144`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDS`	`0x7e800148`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDCS`	`0x7e800200`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBSA0`	`0x7e800204`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBEA0`	`0x7e800208`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBWP`	`0x7e80020c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBCTL`	`0x7e800300`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIBSA1`	`0x7e800304`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIBEA1`	`0x7e800308`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMIDI1`	`0x7e80030c`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBSA1`	`0x7e800310`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMDBEA1`	`0x7e800314`	RW	32	`0xffffffff`	`0000000000`
`CAM0_CAMMISC`	`0x7e800400`	RW	32	`0xffffffff`	`0000000000`

Register details

CAM1

Description

TODO

Info

Name	value	description
base	`0x7e801000`
id	`0x7563616d`

Registers

name	address	type	width	mask	reset
`CAM1_CAMCTL`	`0x7e801000`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMSTA`	`0x7e801004`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMANA`	`0x7e801008`	RW	32	`0xffffffff`	`0x00000777`
`CAM1_CAMPRI`	`0x7e80100c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMCLK`	`0x7e801010`	RW	32	`0xffffffff`	`0x00000002`
`CAM1_CAMCLT`	`0x7e801014`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDAT0`	`0x7e801018`	RW	32	`0xffffffff`	`0x00000002`
`CAM1_CAMDAT1`	`0x7e80101c`	RW	32	`0xffffffff`	`0x00000002`
`CAM1_CAMDAT2`	`0x7e801020`	RW	32	`0xffffffff`	`0x00000002`
`CAM1_CAMDAT3`	`0x7e801024`	RW	32	`0xffffffff`	`0x00000002`
`CAM1_CAMDLT`	`0x7e801028`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMCMP0`	`0x7e80102c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMCMP1`	`0x7e801030`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMCAP0`	`0x7e801034`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMCAP1`	`0x7e801038`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBG0`	`0x7e8010f0`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBG1`	`0x7e8010f4`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBG2`	`0x7e8010f8`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBG3`	`0x7e8010fc`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMICTL`	`0x7e801100`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMISTA`	`0x7e801104`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDI0`	`0x7e801108`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIPIPE`	`0x7e80110c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIBSA0`	`0x7e801110`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIBEA0`	`0x7e801114`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIBLS`	`0x7e801118`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIBWP`	`0x7e80111c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIHWIN`	`0x7e801120`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIHSTA`	`0x7e801124`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIVWIN`	`0x7e801128`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIVSTA`	`0x7e80112c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMICC`	`0x7e801130`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMICS`	`0x7e801134`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDC`	`0x7e801138`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDPO`	`0x7e80113c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDCA`	`0x7e801140`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDCD`	`0x7e801144`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDS`	`0x7e801148`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDCS`	`0x7e801200`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBSA0`	`0x7e801204`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBEA0`	`0x7e801208`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBWP`	`0x7e80120c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBCTL`	`0x7e801300`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIBSA1`	`0x7e801304`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIBEA1`	`0x7e801308`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMIDI1`	`0x7e80130c`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBSA1`	`0x7e801310`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMDBEA1`	`0x7e801314`	RW	32	`0xffffffff`	`0000000000`
`CAM1_CAMMISC`	`0x7e801400`	RW	32	`0xffffffff`	`0000000000`

Register details

CCP2TX

Description

TODO

Info

Name	value	description
base	`0x7e001000`
id	`0x63637032`

Registers

name	address	type	width	mask	reset
`CCP2TX_TC`	`0x7e001000`	RW	32	`0x8000ff07`	`0x0000ff00`
`CCP2TX_TS`	`0x7e001004`	RW	20	`0x000f1f7f`	`0000000000`
`CCP2TX_TAC`	`0x7e001008`	RW	32	`0xffffff0f`	`0x77434307`
`CCP2TX_TPC`	`0x7e00100c`	RW	16	`0x0000ffff`	`0000000000`
`CCP2TX_TSC`	`0x7e001010`	RW	4	`0x0000000f`	`0x00000002`
`CCP2TX_TIC`	`0x7e001014`	RW	8	`0x000000f7`	`0000000000`
`CCP2TX_TTC`	`0x7e001018`	RW	32	`0x80ff1fff`	`0x00000100`
`CCP2TX_TBA`	`0x7e00101c`	RW	30	`0x3fffffff`	`0000000000`
`CCP2TX_TDL`	`0x7e001020`	RW	30	`0x3fffffff`	`0000000000`
`CCP2TX_TD`	`0x7e001024`	RW	8	`0x000000ff`
`CCP2TX_TSPARE`	`0x7e001028`	RW	32	`0xffffffff`

Register details

CCP2TX_TC

Info

Name	value	description
address	`0x7e001000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CCP2TX_TC_TEN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CCP2TX_TC_MEN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CCP2TX_TC_CLKM`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	7	`NA`	`NA`	`NA`
`CCP2TX_TC_TIP`	8	15	`0x0000ff00`	`0xffff00ff`	`0xff`
`missing definiton`	16	30	`NA`	`NA`	`NA`
`CCP2TX_TC_SWR`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

CCP2TX_TS

Info

Name	value	description
address	`0x7e001004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CCP2TX_TS_TXB`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CCP2TX_TS_IEB`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CCP2TX_TS_ARE`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CCP2TX_TS_TUE`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CCP2TX_TS_TFE`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CCP2TX_TS_TFF`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CCP2TX_TS_TFP`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`CCP2TX_TS_TQL`	8	12	`0x00001f00`	`0xffffe0ff`	`0x0`
`missing definiton`	13	15	`NA`	`NA`	`NA`
`CCP2TX_TS_IS`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`CCP2TX_TS_TII`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`CCP2TX_TS_TEI`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`CCP2TX_TS_TQI`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`

CCP2TX_TAC

Info

Name	value	description
address	`0x7e001008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CCP2TX_TAC_ARST`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`CCP2TX_TAC_APD`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`CCP2TX_TAC_BPD`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`CCP2TX_TAC_TPC`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`missing definiton`	4	7	`NA`	`NA`	`NA`
`CCP2TX_TAC_DLAC`	8	15	`0x0000ff00`	`0xffff00ff`	`0x43`
`CCP2TX_TAC_CLAC`	16	23	`0x00ff0000`	`0xff00ffff`	`0x43`
`CCP2TX_TAC_PTATADJ`	24	27	`0x0f000000`	`0xf0ffffff`	`0x7`
`CCP2TX_TAC_CTATADJ`	28	31	`0xf0000000`	`0x0fffffff`	`0x7`

CCP2TX_TPC

Info

Name	value	description
address	`0x7e00100c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CCP2TX_TPC_TNP`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CCP2TX_TPC_TPP`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`CCP2TX_TPC_TPT`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

CCP2TX_TSC

Info

Name	value	description
address	`0x7e001010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CCP2TX_TSC_TSM`	0	3	`0x0000000f`	`0xfffffff0`	`0x2`

CCP2TX_TIC

Info

Name	value	description
address	`0x7e001014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CCP2TX_TIC_TIIE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CCP2TX_TIC_TEIE`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CCP2TX_TIC_TQIE`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`CCP2TX_TIC_TQIT`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`

CCP2TX_TTC

Info

Name	value	description
address	`0x7e001018`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CCP2TX_TTC_LCN`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CCP2TX_TTC_LSC`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`CCP2TX_TTC_LEC`	8	11	`0x00000f00`	`0xfffff0ff`	`0x1`
`CCP2TX_TTC_FSP`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`missing definiton`	13	15	`NA`	`NA`	`NA`
`CCP2TX_TTC_BI`	16	23	`0x00ff0000`	`0xff00ffff`	`0x0`
`missing definiton`	24	30	`NA`	`NA`	`NA`
`CCP2TX_TTC_ATX`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

CCP2TX_TBA

Info

Name	value	description
address	`0x7e00101c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CCP2TX_TBA_ADDR`	0	29	`0x3fffffff`	`0xc0000000`	`0x0`

CCP2TX_TDL

Info

Name	value	description
address	`0x7e001020`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CCP2TX_TDL_LEN`	0	29	`0x3fffffff`	`0xc0000000`	`0x0`

CCP2TX_TD

Info

Name	value	description
address	`0x7e001024`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CCP2TX_TD_TCS`	0	4	`0x0000001f`	`0xffffffe0`
`CCP2TX_TD_IES`	5	6	`0x00000060`	`0xffffff9f`

CM

Description

TODO

Info

Name	value	description
base	`0x7e101000`
id	`0x0000636d`
password	`0x5a000000`

Registers

name	address	type	width	mask	reset
`CM_GNRICCTL`	`0x7e101000`	RW	20	`0x000fffff`	`0000000000`
`CM_GNRICDIV`	`0x7e101004`	RW	24	`0x00ffffff`	`0000000000`
`CM_VPUCTL`	`0x7e101008`	RW	10	`0x000003cf`	`0x00000041`
`CM_VPUDIV`	`0x7e10100c`	RW	24	`0x00fffff0`	`0x00001000`
`CM_SYSCTL`	`0x7e101010`	RW	7	`0x00000040`	`0x00000040`
`CM_SYSDIV`	`0x7e101014`	RO	13	`0x00001000`	`0x00001000`
`CM_PERIACTL`	`0x7e101018`	RW	7	`0x00000040`	`0x00000040`
`CM_PERIADIV`	`0x7e10101c`	RO	13	`0x00001000`	`0x00001000`
`CM_PERIICTL`	`0x7e101020`	RW	7	`0x00000040`	`0000000000`
`CM_PERIIDIV`	`0x7e101024`	RO	13	`0x00001000`	`0x00001000`
`CM_H264CTL`	`0x7e101028`	RW	10	`0x000003ff`	`0x00000040`
`CM_H264DIV`	`0x7e10102c`	RW	16	`0x0000fff0`	`0000000000`
`CM_ISPCTL`	`0x7e101030`	RW	10	`0x000003ff`	`0x00000040`
`CM_ISPDIV`	`0x7e101034`	RW	16	`0x0000fff0`	`0000000000`
`CM_V3DCTL`	`0x7e101038`	RW	10	`0x000003ff`	`0x00000040`
`CM_V3DDIV`	`0x7e10103c`	RW	16	`0x0000fff0`	`0000000000`
`CM_CAM0CTL`	`0x7e101040`	RW	10	`0x000003bf`	`0000000000`
`CM_CAM0DIV`	`0x7e101044`	RW	16	`0x0000fff0`	`0000000000`
`CM_CAM1CTL`	`0x7e101048`	RW	10	`0x000003bf`	`0000000000`
`CM_CAM1DIV`	`0x7e10104c`	RW	16	`0x0000fff0`	`0000000000`
`CM_CCP2CTL`	`0x7e101050`	RW	10	`0x00000397`	`0000000000`
`CM_CCP2DIV`	`0x7e101054`	RO	13	`0x00001000`	`0x00001000`
`CM_DSI0ECTL`	`0x7e101058`	RW	10	`0x000003bf`	`0000000000`
`CM_DSI0EDIV`	`0x7e10105c`	RW	16	`0x0000fff0`	`0000000000`
`CM_DSI0PCTL`	`0x7e101060`	RW	10	`0x0000039f`	`0000000000`
`CM_DSI0PDIV`	`0x7e101064`	RO	13	`0x00001000`	`0x00001000`
`CM_DPICTL`	`0x7e101068`	RW	10	`0x000003bf`	`0000000000`
`CM_DPIDIV`	`0x7e10106c`	RW	16	`0x0000fff0`	`0000000000`
`CM_GP0CTL`	`0x7e101070`	RW	11	`0x000007bf`	`0x00000200`
`CM_GP0DIV`	`0x7e101074`	RW	24	`0x00ffffff`	`0000000000`
`CM_GP1CTL`	`0x7e101078`	RW	11	`0x000007bf`	`0x00000200`
`CM_GP1DIV`	`0x7e10107c`	RW	24	`0x00ffffff`	`0000000000`
`CM_GP2CTL`	`0x7e101080`	RW	10	`0x000003bf`	`0000000000`
`CM_GP2DIV`	`0x7e101084`	RW	24	`0x00ffffff`	`0000000000`
`CM_HSMCTL`	`0x7e101088`	RW	10	`0x000003ff`	`0000000000`
`CM_HSMDIV`	`0x7e10108c`	RW	16	`0x0000fff0`	`0000000000`
`CM_OTPCTL`	`0x7e101090`	RW	10	`0x000003b3`	`0x00000011`
`CM_OTPDIV`	`0x7e101094`	RW	17	`0x0001f000`	`0x00004000`
`CM_PCMCTL`	`0x7e101098`	RW	11	`0x000007bf`	`0x00000200`
`CM_PCMDIV`	`0x7e10109c`	RW	24	`0x00ffffff`	`0000000000`
`CM_PWMCTL`	`0x7e1010a0`	RW	11	`0x000007bf`	`0x00000200`
`CM_PWMDIV`	`0x7e1010a4`	RW	24	`0x00ffffff`	`0000000000`
`CM_SLIMCTL`	`0x7e1010a8`	RW	11	`0x000007bf`	`0x00000200`
`CM_SLIMDIV`	`0x7e1010ac`	RW	24	`0x00ffffff`	`0000000000`
`CM_SMICTL`	`0x7e1010b0`	RW	10	`0x000003bf`	`0000000000`
`CM_SMIDIV`	`0x7e1010b4`	RW	16	`0x0000fff0`	`0000000000`
`CM_TCNTCTL`	`0x7e1010c0`	RW	14	`0x000030cf`	`0000000000`
`CM_TCNTCNT`	`0x7e1010c4`	RW	24	`0x00ffffff`	`0000000000`
`CM_TECCTL`	`0x7e1010c8`	RW	10	`0x000003b3`	`0000000000`
`CM_TECDIV`	`0x7e1010cc`	RW	18	`0x0003f000`	`0000000000`
`CM_TD0CTL`	`0x7e1010d0`	RW	13	`0x00001bff`	`0000000000`
`CM_TD0DIV`	`0x7e1010d4`	RW	24	`0x00ffffff`	`0000000000`
`CM_TD1CTL`	`0x7e1010d8`	RW	13	`0x00001bff`	`0000000000`
`CM_TD1DIV`	`0x7e1010dc`	RW	24	`0x00ffffff`	`0000000000`
`CM_TSENSCTL`	`0x7e1010e0`	RW	10	`0x000003b3`	`0000000000`
`CM_TSENSDIV`	`0x7e1010e4`	RW	17	`0x0001f000`	`0000000000`
`CM_TIMERCTL`	`0x7e1010e8`	RW	10	`0x000003b3`	`0000000000`
`CM_TIMERDIV`	`0x7e1010ec`	RW	18	`0x0003ffff`	`0000000000`
`CM_UARTCTL`	`0x7e1010f0`	RW	10	`0x000003bf`	`0000000000`
`CM_UARTDIV`	`0x7e1010f4`	RW	22	`0x003fffff`	`0000000000`
`CM_VECCTL`	`0x7e1010f8`	RW	10	`0x000003bf`	`0000000000`
`CM_VECDIV`	`0x7e1010fc`	RW	16	`0x0000f000`	`0000000000`
`CM_OSCCOUNT`	`0x7e101100`	RW	24	`0x00ffffff`	`0000000000`
`CM_PLLA`	`0x7e101104`	RW	10	`0x000003ff`	`0x00000300`
`CM_PLLC`	`0x7e101108`	RW	10	`0x000003ff`	`0x00000300`
`CM_PLLD`	`0x7e10110c`	RW	10	`0x000003ff`	`0x00000300`
`CM_PLLH`	`0x7e101110`	RW	10	`0x00000307`	`0x00000300`
`CM_LOCK`	`0x7e101114`	RW	13	`0x00001f1f`	`0000000000`
`CM_EVENT`	`0x7e101118`	RW	24	`0x00ffffff`	`0000000000`
`CM_INTEN`	`0x7e10111c`	RW	24	`0x00ffffff`	`0000000000`
`CM_DSI0HSCK`	`0x7e101120`	RW	1	`0x00000001`	`0000000000`
`CM_CKSM`	`0x7e101124`	RW	22	`0x003fffff`	`0000000000`
`CM_OSCFREQI`	`0x7e101128`	RW	8	`0x000000ff`	`0000000000`
`CM_OSCFREQF`	`0x7e10112c`	RW	20	`0x000fffff`	`0000000000`
`CM_PLLTCTL`	`0x7e101130`	RW	8	`0x000000a7`	`0000000000`
`CM_PLLTCNT0`	`0x7e101134`	RW	24	`0x00ffffff`	`0000000000`
`CM_PLLTCNT1`	`0x7e101138`	RW	24	`0x00ffffff`	`0000000000`
`CM_PLLTCNT2`	`0x7e10113c`	RW	24	`0x00ffffff`	`0000000000`
`CM_PLLTCNT3`	`0x7e101140`	RW	24	`0x00ffffff`	`0000000000`
`CM_TDCLKEN`	`0x7e101144`	RW	14	`0x00003fff`	`0000000000`
`CM_BURSTCTL`	`0x7e101148`	RW	8	`0x000000b0`	`0000000000`
`CM_BURSTCNT`	`0x7e10114c`	RW	24	`0x00ffffff`	`0000000000`
`CM_DSI1ECTL`	`0x7e101158`	RW	10	`0x000003bf`	`0000000000`
`CM_DSI1EDIV`	`0x7e10115c`	RW	16	`0x0000fff0`	`0000000000`
`CM_DSI1PCTL`	`0x7e101160`	RW	10	`0x0000039f`	`0000000000`
`CM_DSI1PDIV`	`0x7e101164`	RO	13	`0x00001000`	`0x00001000`
`CM_DFTCTL`	`0x7e101168`	RW	10	`0x000003bf`	`0000000000`
`CM_DFTDIV`	`0x7e10116c`	RW	17	`0x0001f000`	`0000000000`
`CM_PLLB`	`0x7e101170`	RW	10	`0x00000303`	`0x00000300`
`CM_PULSECTL`	`0x7e101190`	RW	10	`0x000003b3`	`0x00000011`
`CM_PULSEDIV`	`0x7e101194`	RW	24	`0x00fff000`	`0x0001b000`
`CM_SDCCTL`	`0x7e1011a8`	RW	18	`0x0003f3bf`	`0x00004000`
`CM_SDCDIV`	`0x7e1011ac`	RW	18	`0x0003f000`	`0000000000`
`CM_ARMCTL`	`0x7e1011b0`	RW	13	`0x000013bf`	`0x00000004`
`CM_ARMDIV`	`0x7e1011b4`	RO	13	`0x00001000`	`0x00001000`
`CM_AVEOCTL`	`0x7e1011b8`	RW	10	`0x000003bf`	`0000000000`
`CM_AVEODIV`	`0x7e1011bc`	RW	16	`0x0000f000`	`0000000000`
`CM_EMMCCTL`	`0x7e1011c0`	RW	10	`0x000003bf`	`0000000000`
`CM_EMMCDIV`	`0x7e1011c4`	RW	16	`0x0000fff0`	`0000000000`

Register details

CM_GNRICCTL

Info

Name	value	description
address	`0x7e101000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_GNRICCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_GNRICCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_GNRICCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_GNRICCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_GNRICCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_GNRICCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_GNRICCTL_MASH`	9	10	`0x00000600`	`0xfffff9ff`	`0x0`
`CM_GNRICCTL_FLIP`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`

CM_GNRICDIV

Info

Name	value	description
address	`0x7e101004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_GNRICDIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_VPUCTL

Info

Name	value	description
address	`0x7e101008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_VPUCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x1`
`missing definiton`	4	5	`NA`	`NA`	`NA`
`CM_VPUCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`
`CM_VPUCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_VPUCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_VPUCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_VPUDIV

Info

Name	value	description
address	`0x7e10100c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_VPUDIV_DIV`	4	23	`0x00fffff0`	`0xff00000f`	`0x100`

CM_SYSCTL

Info

Name	value	description
address	`0x7e101010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	5	`NA`	`NA`	`NA`
`CM_SYSCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`

CM_SYSDIV

Info

Name	value	description
address	`0x7e101014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_SYSDIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_PERIACTL

Info

Name	value	description
address	`0x7e101018`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	5	`NA`	`NA`	`NA`
`CM_PERIACTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`

CM_PERIADIV

Info

Name	value	description
address	`0x7e10101c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_PERIADIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_PERIICTL

Info

Name	value	description
address	`0x7e101020`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	5	`NA`	`NA`	`NA`
`CM_PERIICTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x0`

CM_PERIIDIV

Info

Name	value	description
address	`0x7e101024`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_PERIIDIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_H264CTL

Info

Name	value	description
address	`0x7e101028`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_H264CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_H264CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_H264CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_H264CTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`
`CM_H264CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_H264CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_H264CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_H264DIV

Info

Name	value	description
address	`0x7e10102c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_H264DIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_ISPCTL

Info

Name	value	description
address	`0x7e101030`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_ISPCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_ISPCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_ISPCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_ISPCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`
`CM_ISPCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_ISPCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_ISPCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_ISPDIV

Info

Name	value	description
address	`0x7e101034`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_ISPDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_V3DCTL

Info

Name	value	description
address	`0x7e101038`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_V3DCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_V3DCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_V3DCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_V3DCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`
`CM_V3DCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_V3DCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_V3DCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_V3DDIV

Info

Name	value	description
address	`0x7e10103c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_V3DDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_CAM0CTL

Info

Name	value	description
address	`0x7e101040`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_CAM0CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_CAM0CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_CAM0CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_CAM0CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_CAM0CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_CAM0CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_CAM0DIV

Info

Name	value	description
address	`0x7e101044`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_CAM0DIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_CAM1CTL

Info

Name	value	description
address	`0x7e101048`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_CAM1CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_CAM1CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_CAM1CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_CAM1CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_CAM1CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_CAM1CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_CAM1DIV

Info

Name	value	description
address	`0x7e10104c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_CAM1DIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_CCP2CTL

Info

Name	value	description
address	`0x7e101050`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_CCP2CTL_SRC`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`CM_CCP2CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`missing definiton`	5	6	`NA`	`NA`	`NA`
`CM_CCP2CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_CCP2CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_CCP2CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_CCP2DIV

Info

Name	value	description
address	`0x7e101054`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_CCP2DIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_DSI0ECTL

Info

Name	value	description
address	`0x7e101058`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_DSI0ECTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_DSI0ECTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_DSI0ECTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_DSI0ECTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_DSI0ECTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_DSI0ECTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI0EDIV

Info

Name	value	description
address	`0x7e10105c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_DSI0EDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_DSI0PCTL

Info

Name	value	description
address	`0x7e101060`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_DSI0PCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_DSI0PCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`missing definiton`	5	6	`NA`	`NA`	`NA`
`CM_DSI0PCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_DSI0PCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_DSI0PCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI0PDIV

Info

Name	value	description
address	`0x7e101064`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_DSI0PDIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_DPICTL

Info

Name	value	description
address	`0x7e101068`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_DPICTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_DPICTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_DPICTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_DPICTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_DPICTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_DPICTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DPIDIV

Info

Name	value	description
address	`0x7e10106c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_DPIDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_GP0CTL

Info

Name	value	description
address	`0x7e101070`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_GP0CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_GP0CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_GP0CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_GP0CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_GP0CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_GP0CTL_MASH`	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_GP0DIV

Info

Name	value	description
address	`0x7e101074`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_GP0DIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_GP1CTL

Info

Name	value	description
address	`0x7e101078`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_GP1CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_GP1CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_GP1CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_GP1CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_GP1CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_GP1CTL_MASH`	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_GP1DIV

Info

Name	value	description
address	`0x7e10107c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_GP1DIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_GP2CTL

Info

Name	value	description
address	`0x7e101080`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_GP2CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_GP2CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_GP2CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_GP2CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_GP2CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_GP2CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_GP2DIV

Info

Name	value	description
address	`0x7e101084`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_GP2DIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_HSMCTL

Info

Name	value	description
address	`0x7e101088`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_HSMCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_HSMCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_HSMCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_HSMCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_HSMCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_HSMCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_HSMCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_HSMDIV

Info

Name	value	description
address	`0x7e10108c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_HSMDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_OTPCTL

Info

Name	value	description
address	`0x7e101090`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_OTPCTL_SRC`	0	1	`0x00000003`	`0xfffffffc`	`0x1`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`CM_OTPCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x1`
`CM_OTPCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_OTPCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_OTPCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_OTPCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_OTPDIV

Info

Name	value	description
address	`0x7e101094`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_OTPDIV_DIV`	12	16	`0x0001f000`	`0xfffe0fff`	`0x4`

CM_PCMCTL

Info

Name	value	description
address	`0x7e101098`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PCMCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_PCMCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_PCMCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_PCMCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_PCMCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_PCMCTL_MASH`	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_PCMDIV

Info

Name	value	description
address	`0x7e10109c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_PCMDIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PWMCTL

Info

Name	value	description
address	`0x7e1010a0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PWMCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_PWMCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_PWMCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_PWMCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_PWMCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_PWMCTL_MASH`	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_PWMDIV

Info

Name	value	description
address	`0x7e1010a4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_PWMDIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_SLIMCTL

Info

Name	value	description
address	`0x7e1010a8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_SLIMCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_SLIMCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_SLIMCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_SLIMCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_SLIMCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_SLIMCTL_MASH`	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_SLIMDIV

Info

Name	value	description
address	`0x7e1010ac`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_SLIMDIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_SMICTL

Info

Name	value	description
address	`0x7e1010b0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_SMICTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_SMICTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_SMICTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_SMICTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_SMICTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_SMICTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_SMIDIV

Info

Name	value	description
address	`0x7e1010b4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_SMIDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_TCNTCTL

Info

Name	value	description
address	`0x7e1010c0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TCNTCTL_SRC0`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`missing definiton`	4	5	`NA`	`NA`	`NA`
`CM_TCNTCTL_KILL`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_TCNTCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`missing definiton`	8	11	`NA`	`NA`	`NA`
`CM_TCNTCTL_SRC1`	12	13	`0x00003000`	`0xffffcfff`	`0x0`

CM_TCNTCNT

Info

Name	value	description
address	`0x7e1010c4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_TCNTCNT_CNT`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TECCTL

Info

Name	value	description
address	`0x7e1010c8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TECCTL_SRC`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`CM_TECCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_TECCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_TECCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_TECCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_TECCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_TECDIV

Info

Name	value	description
address	`0x7e1010cc`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_TECDIV_DIV`	12	17	`0x0003f000`	`0xfffc0fff`	`0x0`

CM_TD0CTL

Info

Name	value	description
address	`0x7e1010d0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TD0CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_TD0CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_TD0CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_TD0CTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_TD0CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_TD0CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_TD0CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`missing definiton`	10	10	`NA`	`NA`	`NA`
`CM_TD0CTL_FLIP`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`CM_TD0CTL_STEP`	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_TD0DIV

Info

Name	value	description
address	`0x7e1010d4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_TD0DIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TD1CTL

Info

Name	value	description
address	`0x7e1010d8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TD1CTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_TD1CTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_TD1CTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_TD1CTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_TD1CTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_TD1CTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_TD1CTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`missing definiton`	10	10	`NA`	`NA`	`NA`
`CM_TD1CTL_FLIP`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`CM_TD1CTL_STEP`	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_TD1DIV

Info

Name	value	description
address	`0x7e1010dc`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_TD1DIV_DIV`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TSENSCTL

Info

Name	value	description
address	`0x7e1010e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TSENSCTL_SRC`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`CM_TSENSCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_TSENSCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_TSENSCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_TSENSCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_TSENSCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_TSENSDIV

Info

Name	value	description
address	`0x7e1010e4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_TSENSDIV_DIV`	12	16	`0x0001f000`	`0xfffe0fff`	`0x0`

CM_TIMERCTL

Info

Name	value	description
address	`0x7e1010e8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TIMERCTL_SRC`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`CM_TIMERCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_TIMERCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_TIMERCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_TIMERCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_TIMERCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_TIMERDIV

Info

Name	value	description
address	`0x7e1010ec`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_TIMERDIV_DIV`	0	17	`0x0003ffff`	`0xfffc0000`	`0x0`

CM_UARTCTL

Info

Name	value	description
address	`0x7e1010f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_UARTCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_UARTCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_UARTCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_UARTCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_UARTCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_UARTCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_UARTDIV

Info

Name	value	description
address	`0x7e1010f4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_UARTDIV_DIV`	0	21	`0x003fffff`	`0xffc00000`	`0x0`

CM_VECCTL

Info

Name	value	description
address	`0x7e1010f8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_VECCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_VECCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_VECCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_VECCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_VECCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_VECCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_VECDIV

Info

Name	value	description
address	`0x7e1010fc`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_VECDIV_DIV`	12	15	`0x0000f000`	`0xffff0fff`	`0x0`

CM_OSCCOUNT

Info

Name	value	description
address	`0x7e101100`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_OSCCOUNT_NUM`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLA

Info

Name	value	description
address	`0x7e101104`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PLLA_LOADDSI0`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_PLLA_HOLDDSI0`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_PLLA_LOADCCP2`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_PLLA_HOLDCCP2`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_PLLA_LOADCORE`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_PLLA_HOLDCORE`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_PLLA_LOADPER`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_PLLA_HOLDPER`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_PLLA_ANARST`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`CM_PLLA_DIGRST`	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PLLC

Info

Name	value	description
address	`0x7e101108`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PLLC_LOADCORE0`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_PLLC_HOLDCORE0`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_PLLC_LOADCORE1`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_PLLC_HOLDCORE1`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_PLLC_LOADCORE2`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_PLLC_HOLDCORE2`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_PLLC_LOADPER`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_PLLC_HOLDPER`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_PLLC_ANARST`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`CM_PLLC_DIGRST`	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PLLD

Info

Name	value	description
address	`0x7e10110c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PLLD_LOADDSI0`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_PLLD_HOLDDSI0`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_PLLD_LOADDSI1`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_PLLD_HOLDDSI1`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_PLLD_LOADCORE`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_PLLD_HOLDCORE`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_PLLD_LOADPER`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_PLLD_HOLDPER`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_PLLD_ANARST`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`CM_PLLD_DIGRST`	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PLLH

Info

Name	value	description
address	`0x7e101110`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PLLH_LOADPIX`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_PLLH_LOADAUX`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_PLLH_LOADRCAL`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	7	`NA`	`NA`	`NA`
`CM_PLLH_ANARST`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`CM_PLLH_DIGRST`	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_LOCK

Info

Name	value	description
address	`0x7e101114`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_LOCK_LOCKA`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_LOCK_LOCKB`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_LOCK_LOCKC`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_LOCK_LOCKD`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_LOCK_LOCKH`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`CM_LOCK_FLOCKA`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_LOCK_FLOCKB`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`CM_LOCK_FLOCKC`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`CM_LOCK_FLOCKD`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`CM_LOCK_FLOCKH`	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_EVENT

Info

Name	value	description
address	`0x7e101118`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_EVENT_GAINA`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_EVENT_GAINB`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_EVENT_GAINC`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_EVENT_GAIND`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_EVENT_GAINH`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_EVENT_LOSSA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_EVENT_LOSSB`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_EVENT_LOSSC`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_EVENT_LOSSD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_EVENT_LOSSH`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`CM_EVENT_FGAINA`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`CM_EVENT_FGAINB`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`CM_EVENT_FGAINC`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`CM_EVENT_FGAIND`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`CM_EVENT_FLOSSA`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`CM_EVENT_FLOSSB`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`CM_EVENT_FLOSSC`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`CM_EVENT_FLOSSD`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`CM_EVENT_BADPASS`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`CM_EVENT_WRFAIL`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`CM_EVENT_A2WDONE`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`CM_EVENT_OCDONE`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`CM_EVENT_RESUS`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`CM_EVENT_BURSTDONE`	23	23	`0x00800000`	`0xff7fffff`	`0x0`

CM_INTEN

Info

Name	value	description
address	`0x7e10111c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_INTEN_GAINA`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_INTEN_GAINB`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_INTEN_GAINC`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_INTEN_GAIND`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_INTEN_GAINH`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_INTEN_LOSSA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_INTEN_LOSSB`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_INTEN_LOSSC`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_INTEN_LOSSD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_INTEN_LOSSH`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`CM_INTEN_FGAINA`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`CM_INTEN_FGAINB`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`CM_INTEN_FGAINC`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`CM_INTEN_FGAIND`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`CM_INTEN_FLOSSA`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`CM_INTEN_FLOSSB`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`CM_INTEN_FLOSSC`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`CM_INTEN_FLOSSD`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`CM_INTEN_BADPASS`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`CM_INTEN_WRFAIL`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`CM_INTEN_A2WDONE`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`CM_INTEN_OCDONE`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`CM_INTEN_RESUS`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`CM_INTEN_BURSTDONE`	23	23	`0x00800000`	`0xff7fffff`	`0x0`

CM_DSI0HSCK

Info

Name	value	description
address	`0x7e101120`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_DSI0HSCK_SELPLLD`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

CM_CKSM

Info

Name	value	description
address	`0x7e101124`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_CKSM_STATE`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`CM_CKSM_FRCE`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`CM_CKSM_CFG`	16	17	`0x00030000`	`0xfffcffff`	`0x0`
`CM_CKSM_OSC`	18	19	`0x000c0000`	`0xfff3ffff`	`0x0`
`CM_CKSM_AUTO`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`CM_CKSM_STEP`	21	21	`0x00200000`	`0xffdfffff`	`0x0`

CM_OSCFREQI

Info

Name	value	description
address	`0x7e101128`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_OSCFREQI_INT`	0	7	`0x000000ff`	`0xffffff00`	`0x0`

CM_OSCFREQF

Info

Name	value	description
address	`0x7e10112c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_OSCFREQF_FRAC`	0	19	`0x000fffff`	`0xfff00000`	`0x0`

CM_PLLTCTL

Info

Name	value	description
address	`0x7e101130`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PLLTCTL_SRC`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`missing definiton`	3	4	`NA`	`NA`	`NA`
`CM_PLLTCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_PLLTCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`

CM_PLLTCNT0

Info

Name	value	description
address	`0x7e101134`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_PLLTCNT0_CNT`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLTCNT1

Info

Name	value	description
address	`0x7e101138`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_PLLTCNT1_CNT`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLTCNT2

Info

Name	value	description
address	`0x7e10113c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_PLLTCNT2_CNT`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLTCNT3

Info

Name	value	description
address	`0x7e101140`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_PLLTCNT3_CNT`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TDCLKEN

Info

Name	value	description
address	`0x7e101144`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_TDCLKEN_PLLABYP`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_TDCLKEN_PLLBBYP`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`CM_TDCLKEN_PLLCBYP`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`CM_TDCLKEN_PLLDBYP`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`CM_TDCLKEN_PLLADIV2`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_TDCLKEN_PLLBDIV2`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`CM_TDCLKEN_PLLCDIV2`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`CM_TDCLKEN_PLLDDIV2`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_TDCLKEN_HDMIBYP`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_TDCLKEN_MPHIWDFT`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`CM_TDCLKEN_MPHIRDFT`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`CM_TDCLKEN_USBDFT`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`CM_TDCLKEN_SLIMDFT`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`CM_TDCLKEN_IMAGETD`	13	13	`0x00002000`	`0xffffdfff`	`0x0`

CM_BURSTCTL

Info

Name	value	description
address	`0x7e101148`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_BURSTCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_BURSTCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_BURSTCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`

CM_BURSTCNT

Info

Name	value	description
address	`0x7e10114c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CM_BURSTCNT_CNT`	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_DSI1ECTL

Info

Name	value	description
address	`0x7e101158`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_DSI1ECTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_DSI1ECTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_DSI1ECTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_DSI1ECTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_DSI1ECTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_DSI1ECTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI1EDIV

Info

Name	value	description
address	`0x7e10115c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_DSI1EDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_DSI1PCTL

Info

Name	value	description
address	`0x7e101160`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_DSI1PCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_DSI1PCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`missing definiton`	5	6	`NA`	`NA`	`NA`
`CM_DSI1PCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_DSI1PCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_DSI1PCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI1PDIV

Info

Name	value	description
address	`0x7e101164`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_DSI1PDIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_DFTCTL

Info

Name	value	description
address	`0x7e101168`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_DFTCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_DFTCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_DFTCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_DFTCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_DFTCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_DFTCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DFTDIV

Info

Name	value	description
address	`0x7e10116c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_DFTDIV_DIV`	12	16	`0x0001f000`	`0xfffe0fff`	`0x0`

CM_PLLB

Info

Name	value	description
address	`0x7e101170`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PLLB_LOADARM`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`CM_PLLB_HOLDARM`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`missing definiton`	2	7	`NA`	`NA`	`NA`
`CM_PLLB_ANARST`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`CM_PLLB_DIGRST`	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PULSECTL

Info

Name	value	description
address	`0x7e101190`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_PULSECTL_SRC`	0	1	`0x00000003`	`0xfffffffc`	`0x1`
`missing definiton`	2	3	`NA`	`NA`	`NA`
`CM_PULSECTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x1`
`CM_PULSECTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_PULSECTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_PULSECTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_PULSECTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_PULSEDIV

Info

Name	value	description
address	`0x7e101194`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_PULSEDIV_DIV`	12	23	`0x00fff000`	`0xff000fff`	`0x1b`

CM_SDCCTL

Info

Name	value	description
address	`0x7e1011a8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_SDCCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_SDCCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_SDCCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_SDCCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_SDCCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_SDCCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`missing definiton`	10	11	`NA`	`NA`	`NA`
`CM_SDCCTL_CTRL`	12	15	`0x0000f000`	`0xffff0fff`	`0x4`
`CM_SDCCTL_ACCPT`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`CM_SDCCTL_UPDATE`	17	17	`0x00020000`	`0xfffdffff`	`0x0`

CM_SDCDIV

Info

Name	value	description
address	`0x7e1011ac`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_SDCDIV_DIV`	12	17	`0x0003f000`	`0xfffc0fff`	`0x0`

CM_ARMCTL

Info

Name	value	description
address	`0x7e1011b0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_ARMCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x4`
`CM_ARMCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_ARMCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_ARMCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_ARMCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_ARMCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`missing definiton`	10	11	`NA`	`NA`	`NA`
`CM_ARMCTL_AXIHALF`	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_ARMDIV

Info

Name	value	description
address	`0x7e1011b4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_ARMDIV_DIV`	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_AVEOCTL

Info

Name	value	description
address	`0x7e1011b8`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_AVEOCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_AVEOCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_AVEOCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_AVEOCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_AVEOCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_AVEOCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_AVEODIV

Info

Name	value	description
address	`0x7e1011bc`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	11	`NA`	`NA`	`NA`
`CM_AVEODIV_DIV`	12	15	`0x0000f000`	`0xffff0fff`	`0x0`

CM_EMMCCTL

Info

Name	value	description
address	`0x7e1011c0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CM_EMMCCTL_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CM_EMMCCTL_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`CM_EMMCCTL_KILL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`CM_EMMCCTL_BUSY`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`CM_EMMCCTL_BUSYD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`CM_EMMCCTL_FRAC`	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_EMMCDIV

Info

Name	value	description
address	`0x7e1011c4`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	3	`NA`	`NA`	`NA`
`CM_EMMCDIV_DIV`	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CMI

Description

TODO

Info

Name	value	description
base	`0x7e802000`
id	`0x00636d69`
password	`0x5a000000`

Registers

name	address	type	width	mask	reset
`CMI_CAM0`	`0x7e802000`	RW	6	`0x0000003f`	`0000000000`
`CMI_CAM1`	`0x7e802004`	RW	10	`0x000003ff`	`0000000000`
`CMI_CAMTEST`	`0x7e802008`	RW	5	`0x0000001f`	`0000000000`
`CMI_USBCTL`	`0x7e802010`	RW	7	`0x00000040`	`0x00000040`

Register details

CMI_CAM0

Info

Name	value	description
address	`0x7e802000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CMI_CAM0_HSSRC`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`CMI_CAM0_RX0SRC`	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
`CMI_CAM0_RX1SRC`	4	5	`0x00000030`	`0xffffffcf`	`0x0`

CMI_CAM1

Info

Name	value	description
address	`0x7e802004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`CMI_CAM1_HSSRC`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`CMI_CAM1_RX0SRC`	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
`CMI_CAM1_RX1SRC`	4	5	`0x00000030`	`0xffffffcf`	`0x0`
`CMI_CAM1_RX2SRC`	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
`CMI_CAM1_RX3SRC`	8	9	`0x00000300`	`0xfffffcff`	`0x0`

CMI_CAMTEST

Info

Name	value	description
address	`0x7e802008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`CMI_CAMTEST_SRC`	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
`CMI_CAMTEST_ENAB`	4	4	`0x00000010`	`0xffffffef`	`0x0`

CMI_USBCTL

Info

Name	value	description
address	`0x7e802010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	5	`NA`	`NA`	`NA`
`CMI_USBCTL_GATE`	6	6	`0x00000040`	`0xffffffbf`	`0x1`

CPG

Description

TODO

Info

Name	value	description
base	`0x7e211000`
id	`0x67706320`

Registers

name	address	type	width	mask
`CPG_Config`	`0x7e211000`	RW	32	`0xffffffff`
`CPG_IntStatus`	`0x7e211004`	RW	32	`0xffffffff`
`CPG_Trigger`	`0x7e211008`	RW	2	`0x00000003`
`CPG_Param0`	`0x7e211010`	RW	32	`0xffffffff`
`CPG_Param1`	`0x7e211014`	RW	32	`0xffffffff`
`CPG_Param2`	`0x7e211018`	RW	32	`0xffffffff`
`CPG_Param3`	`0x7e21101c`	RW	32	`0xffffffff`
`CPG_Debug0`	`0x7e211040`	RW	32	`0xffffffff`
`CPG_Debug1`	`0x7e211044`	RW	32	`0xffffffff`
`CPG_Debug2`	`0x7e211048`	RW	32	`0xffffffff`
`CPG_Debug3`	`0x7e21104c`	RW	32	`0xffffffff`

Register details

DMA

Description

TODO

Info

Name	value	description
base	`0x7e007fe0`

unknown defined macro

define	type	description
`DMA_CB_2DSTR`	MACRO
`DMA_CB_ADDR`	MACRO
`DMA_CB_DA`	MACRO
`DMA_CB_NEXT`	MACRO
`DMA_CB_SA`	MACRO
`DMA_CB_TI`	MACRO
`DMA_CB_TL`	MACRO
`DMA_CH_BASE`	MACRO
`DMA_CS`	MACRO
`DMA_CS_ABORT`	UNKNOWN
`DMA_CS_ACTIVE`	UNKNOWN
`DMA_CS_DIS_DBS_PAUSE`	UNKNOWN
`DMA_CS_DREQ`	UNKNOWN
`DMA_CS_DREQ_PAUSED`	UNKNOWN
`DMA_CS_END`	UNKNOWN
`DMA_CS_ERROR`	UNKNOWN
`DMA_CS_INT`	UNKNOWN
`DMA_CS_PANIC_PRIORITY`	UNKNOWN
`DMA_CS_PAUSED`	UNKNOWN
`DMA_CS_PRIORITY`	UNKNOWN
`DMA_CS_RESET`	UNKNOWN
`DMA_CS_WAITING_FOR_LAST_WRITE`	UNKNOWN
`DMA_CS_WAIT_FOR_LAST_WRITE`	UNKNOWN
`DMA_DEBUG`	MACRO
`DMA_DEBUG_FIFO_ERR`	UNKNOWN
`DMA_DEBUG_ID`	UNKNOWN
`DMA_DEBUG_OUTSTANDING_WRITES`	UNKNOWN
`DMA_DEBUG_READ_ERR`	UNKNOWN
`DMA_DEBUG_READ_LAST_ERR`	UNKNOWN
`DMA_DEBUG_STATE`	UNKNOWN
`DMA_DEBUG_VERSION`	UNKNOWN
`DMA_INTERRUPT`	MACRO
`DMA_REG`	MACRO
`DMA_TI_BURST_N`	MACRO
`DMA_TI_D_128`	UNKNOWN
`DMA_TI_D_32`	UNKNOWN
`DMA_TI_D_DREQ`	UNKNOWN
`DMA_TI_D_IGNORE`	UNKNOWN
`DMA_TI_D_INC`	UNKNOWN
`DMA_TI_D_WIDTH`	UNKNOWN
`DMA_TI_INT`	UNKNOWN
`DMA_TI_NO_WIDE_BURSTS`	UNKNOWN
`DMA_TI_PERMAP`	UNKNOWN
`DMA_TI_PER_MAP`	MACRO
`DMA_TI_S_128`	UNKNOWN
`DMA_TI_S_32`	UNKNOWN
`DMA_TI_S_DREQ`	UNKNOWN
`DMA_TI_S_IGNORE`	UNKNOWN
`DMA_TI_S_INC`	UNKNOWN
`DMA_TI_S_WIDTH`	UNKNOWN
`DMA_TI_TDMODE`	UNKNOWN
`DMA_TI_WAITS`	MACRO
`DMA_TI_WAIT_RESP`	UNKNOWN

Registers

name	address	type	width	mask	reset	description
`DMA_INT_STATUS`	`0x7e007fe0`	RO	16	`0x0000ffff`	`0000000000`
`DMA_ENABLE`	`0x7e007ff0`	RW	15	`0x00007fff`	`0x00007fff`

Register details

DMA_INT_STATUS

Info

Name	value	description
address	`0x7e007fe0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA_INT_STATUS_INT0`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA_INT_STATUS_INT1`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA_INT_STATUS_INT2`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA_INT_STATUS_INT3`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA_INT_STATUS_INT4`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA_INT_STATUS_INT5`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA_INT_STATUS_INT6`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`DMA_INT_STATUS_INT7`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`DMA_INT_STATUS_INT8`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`DMA_INT_STATUS_INT9`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`DMA_INT_STATUS_INT10`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`DMA_INT_STATUS_INT11`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`DMA_INT_STATUS_INT12`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`DMA_INT_STATUS_INT13`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`DMA_INT_STATUS_INT14`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`DMA_INT_STATUS_INT15`	15	15	`0x00008000`	`0xffff7fff`	`0x0`

DMA_ENABLE

Info

Name	value	description
address	`0x7e007ff0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA_ENABLE_EN0`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`DMA_ENABLE_EN1`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`DMA_ENABLE_EN2`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`DMA_ENABLE_EN3`	3	3	`0x00000008`	`0xfffffff7`	`0x1`
`DMA_ENABLE_EN4`	4	4	`0x00000010`	`0xffffffef`	`0x1`
`DMA_ENABLE_EN5`	5	5	`0x00000020`	`0xffffffdf`	`0x1`
`DMA_ENABLE_EN6`	6	6	`0x00000040`	`0xffffffbf`	`0x1`
`DMA_ENABLE_EN7`	7	7	`0x00000080`	`0xffffff7f`	`0x1`
`DMA_ENABLE_EN8`	8	8	`0x00000100`	`0xfffffeff`	`0x1`
`DMA_ENABLE_EN9`	9	9	`0x00000200`	`0xfffffdff`	`0x1`
`DMA_ENABLE_EN10`	10	10	`0x00000400`	`0xfffffbff`	`0x1`
`DMA_ENABLE_EN11`	11	11	`0x00000800`	`0xfffff7ff`	`0x1`
`DMA_ENABLE_EN12`	12	12	`0x00001000`	`0xffffefff`	`0x1`
`DMA_ENABLE_EN13`	13	13	`0x00002000`	`0xffffdfff`	`0x1`
`DMA_ENABLE_EN14`	14	14	`0x00004000`	`0xffffbfff`	`0x1`

DMA0

Description

TODO

Info

Name	value	description
base	`0x7e007000`

Registers

name	address	type	width	mask	reset
`DMA0_CS`	`0x7e007000`	RW	32	`0xf0ff017f`	`0000000000`
`DMA0_CONBLK_AD`	`0x7e007004`	RW	32	`0xffffffe0`	`0000000000`
`DMA0_TI`	`0x7e007008`	RO	27	`0x07fffffb`
`DMA0_SOURCE_AD`	`0x7e00700c`	RO	32	`0xffffffff`
`DMA0_DEST_AD`	`0x7e007010`	RO	32	`0xffffffff`
`DMA0_TXFR_LEN`	`0x7e007014`	RO	30	`0x3fffffff`
`DMA0_STRIDE`	`0x7e007018`	RO	32	`0xffffffff`
`DMA0_NEXTCONBK`	`0x7e00701c`	RO	32	`0xffffffe0`
`DMA0_DEBUG`	`0x7e007020`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA0_CS

Info

Name	value	description
address	`0x7e007000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA0_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA0_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA0_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA0_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA0_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA0_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA0_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA0_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA0_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA0_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA0_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA0_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA0_CONBLK_AD

Info

Name	value	description
address	`0x7e007004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA0_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA0_TI

Info

Name	value	description
address	`0x7e007008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA0_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA0_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA0_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA0_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA0_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA0_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA0_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA0_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA0_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA0_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA0_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA0_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA0_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA0_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA0_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA0_SOURCE_AD

Info

Name	value	description
address	`0x7e00700c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA0_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA0_DEST_AD

Info

Name	value	description
address	`0x7e007010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA0_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA0_TXFR_LEN

Info

Name	value	description
address	`0x7e007014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA0_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA0_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA0_STRIDE

Info

Name	value	description
address	`0x7e007018`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA0_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA0_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA0_NEXTCONBK

Info

Name	value	description
address	`0x7e00701c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA0_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA0_DEBUG

Info

Name	value	description
address	`0x7e007020`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA0_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA0_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA0_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA0_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA0_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA0_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA0_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA0_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA1

Description

TODO

Info

Name	value	description
base	`0x7e007100`

Registers

name	address	type	width	mask	reset
`DMA1_CS`	`0x7e007100`	RW	32	`0xf0ff017f`	`0000000000`
`DMA1_CONBLK_AD`	`0x7e007104`	RW	32	`0xffffffe0`	`0000000000`
`DMA1_TI`	`0x7e007108`	RO	27	`0x07fffffb`
`DMA1_SOURCE_AD`	`0x7e00710c`	RO	32	`0xffffffff`
`DMA1_DEST_AD`	`0x7e007110`	RO	32	`0xffffffff`
`DMA1_TXFR_LEN`	`0x7e007114`	RO	30	`0x3fffffff`
`DMA1_STRIDE`	`0x7e007118`	RO	32	`0xffffffff`
`DMA1_NEXTCONBK`	`0x7e00711c`	RO	32	`0xffffffe0`
`DMA1_DEBUG`	`0x7e007120`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA1_CS

Info

Name	value	description
address	`0x7e007100`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA1_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA1_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA1_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA1_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA1_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA1_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA1_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA1_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA1_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA1_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA1_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA1_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA1_CONBLK_AD

Info

Name	value	description
address	`0x7e007104`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA1_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA1_TI

Info

Name	value	description
address	`0x7e007108`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA1_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA1_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA1_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA1_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA1_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA1_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA1_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA1_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA1_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA1_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA1_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA1_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA1_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA1_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA1_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA1_SOURCE_AD

Info

Name	value	description
address	`0x7e00710c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA1_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA1_DEST_AD

Info

Name	value	description
address	`0x7e007110`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA1_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA1_TXFR_LEN

Info

Name	value	description
address	`0x7e007114`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA1_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA1_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA1_STRIDE

Info

Name	value	description
address	`0x7e007118`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA1_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA1_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA1_NEXTCONBK

Info

Name	value	description
address	`0x7e00711c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA1_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA1_DEBUG

Info

Name	value	description
address	`0x7e007120`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA1_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA1_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA1_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA1_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA1_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA1_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA1_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA1_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA10

Description

TODO

Info

Name	value	description
base	`0x7e007a00`

Registers

name	address	type	width	mask	reset
`DMA10_CS`	`0x7e007a00`	RW	32	`0xf0ff017f`	`0000000000`
`DMA10_CONBLK_AD`	`0x7e007a04`	RW	32	`0xffffffe0`	`0000000000`
`DMA10_TI`	`0x7e007a08`	RO	26	`0x03fffff9`
`DMA10_SOURCE_AD`	`0x7e007a0c`	RO	32	`0xffffffff`
`DMA10_DEST_AD`	`0x7e007a10`	RO	32	`0xffffffff`
`DMA10_TXFR_LEN`	`0x7e007a14`	RO	16	`0x0000ffff`
`DMA10_NEXTCONBK`	`0x7e007a1c`	RO	32	`0xffffffe0`
`DMA10_DEBUG`	`0x7e007a20`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA10_CS

Info

Name	value	description
address	`0x7e007a00`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA10_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA10_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA10_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA10_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA10_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA10_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA10_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA10_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA10_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA10_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA10_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA10_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA10_CONBLK_AD

Info

Name	value	description
address	`0x7e007a04`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA10_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA10_TI

Info

Name	value	description
address	`0x7e007a08`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA10_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA10_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA10_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA10_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA10_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA10_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA10_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA10_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA10_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA10_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA10_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA10_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA10_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA10_SOURCE_AD

Info

Name	value	description
address	`0x7e007a0c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA10_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA10_DEST_AD

Info

Name	value	description
address	`0x7e007a10`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA10_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA10_TXFR_LEN

Info

Name	value	description
address	`0x7e007a14`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA10_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA10_NEXTCONBK

Info

Name	value	description
address	`0x7e007a1c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA10_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA10_DEBUG

Info

Name	value	description
address	`0x7e007a20`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA10_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA10_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA10_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA10_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA10_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA10_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA10_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA10_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA11

Description

TODO

Info

Name	value	description
base	`0x7e007b00`

Registers

name	address	type	width	mask	reset
`DMA11_CS`	`0x7e007b00`	RW	32	`0xf0ff017f`	`0000000000`
`DMA11_CONBLK_AD`	`0x7e007b04`	RW	32	`0xffffffe0`	`0000000000`
`DMA11_TI`	`0x7e007b08`	RO	26	`0x03fffff9`
`DMA11_SOURCE_AD`	`0x7e007b0c`	RO	32	`0xffffffff`
`DMA11_DEST_AD`	`0x7e007b10`	RO	32	`0xffffffff`
`DMA11_TXFR_LEN`	`0x7e007b14`	RO	16	`0x0000ffff`
`DMA11_NEXTCONBK`	`0x7e007b1c`	RO	32	`0xffffffe0`
`DMA11_DEBUG`	`0x7e007b20`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA11_CS

Info

Name	value	description
address	`0x7e007b00`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA11_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA11_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA11_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA11_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA11_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA11_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA11_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA11_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA11_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA11_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA11_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA11_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA11_CONBLK_AD

Info

Name	value	description
address	`0x7e007b04`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA11_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA11_TI

Info

Name	value	description
address	`0x7e007b08`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA11_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA11_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA11_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA11_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA11_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA11_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA11_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA11_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA11_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA11_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA11_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA11_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA11_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA11_SOURCE_AD

Info

Name	value	description
address	`0x7e007b0c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA11_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA11_DEST_AD

Info

Name	value	description
address	`0x7e007b10`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA11_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA11_TXFR_LEN

Info

Name	value	description
address	`0x7e007b14`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA11_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA11_NEXTCONBK

Info

Name	value	description
address	`0x7e007b1c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA11_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA11_DEBUG

Info

Name	value	description
address	`0x7e007b20`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA11_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA11_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA11_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA11_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA11_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA11_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA11_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA11_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA12

Description

TODO

Info

Name	value	description
base	`0x7e007c00`

Registers

name	address	type	width	mask	reset
`DMA12_CS`	`0x7e007c00`	RW	32	`0xf0ff017f`	`0000000000`
`DMA12_CONBLK_AD`	`0x7e007c04`	RW	32	`0xffffffe0`	`0000000000`
`DMA12_TI`	`0x7e007c08`	RO	26	`0x03fffff9`
`DMA12_SOURCE_AD`	`0x7e007c0c`	RO	32	`0xffffffff`
`DMA12_DEST_AD`	`0x7e007c10`	RO	32	`0xffffffff`
`DMA12_TXFR_LEN`	`0x7e007c14`	RO	16	`0x0000ffff`
`DMA12_NEXTCONBK`	`0x7e007c1c`	RO	32	`0xffffffe0`
`DMA12_DEBUG`	`0x7e007c20`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA12_CS

Info

Name	value	description
address	`0x7e007c00`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA12_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA12_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA12_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA12_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA12_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA12_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA12_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA12_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA12_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA12_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA12_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA12_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA12_CONBLK_AD

Info

Name	value	description
address	`0x7e007c04`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA12_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA12_TI

Info

Name	value	description
address	`0x7e007c08`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA12_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA12_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA12_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA12_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA12_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA12_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA12_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA12_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA12_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA12_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA12_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA12_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA12_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA12_SOURCE_AD

Info

Name	value	description
address	`0x7e007c0c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA12_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA12_DEST_AD

Info

Name	value	description
address	`0x7e007c10`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA12_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA12_TXFR_LEN

Info

Name	value	description
address	`0x7e007c14`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA12_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA12_NEXTCONBK

Info

Name	value	description
address	`0x7e007c1c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA12_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA12_DEBUG

Info

Name	value	description
address	`0x7e007c20`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA12_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA12_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA12_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA12_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA12_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA12_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA12_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA12_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA13

Description

TODO

Info

Name	value	description
base	`0x7e007d00`

Registers

name	address	type	width	mask	reset
`DMA13_CS`	`0x7e007d00`	RW	32	`0xf0ff017f`	`0000000000`
`DMA13_CONBLK_AD`	`0x7e007d04`	RW	32	`0xffffffe0`	`0000000000`
`DMA13_TI`	`0x7e007d08`	RO	26	`0x03fffff9`
`DMA13_SOURCE_AD`	`0x7e007d0c`	RO	32	`0xffffffff`
`DMA13_DEST_AD`	`0x7e007d10`	RO	32	`0xffffffff`
`DMA13_TXFR_LEN`	`0x7e007d14`	RO	16	`0x0000ffff`
`DMA13_NEXTCONBK`	`0x7e007d1c`	RO	32	`0xffffffe0`
`DMA13_DEBUG`	`0x7e007d20`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA13_CS

Info

Name	value	description
address	`0x7e007d00`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA13_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA13_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA13_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA13_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA13_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA13_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA13_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA13_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA13_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA13_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA13_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA13_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA13_CONBLK_AD

Info

Name	value	description
address	`0x7e007d04`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA13_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA13_TI

Info

Name	value	description
address	`0x7e007d08`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA13_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA13_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA13_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA13_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA13_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA13_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA13_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA13_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA13_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA13_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA13_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA13_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA13_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA13_SOURCE_AD

Info

Name	value	description
address	`0x7e007d0c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA13_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA13_DEST_AD

Info

Name	value	description
address	`0x7e007d10`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA13_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA13_TXFR_LEN

Info

Name	value	description
address	`0x7e007d14`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA13_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA13_NEXTCONBK

Info

Name	value	description
address	`0x7e007d1c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA13_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA13_DEBUG

Info

Name	value	description
address	`0x7e007d20`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA13_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA13_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA13_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA13_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA13_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA13_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA13_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA13_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA14

Description

TODO

Info

Name	value	description
base	`0x7e007e00`

Registers

name	address	type	width	mask	reset
`DMA14_CS`	`0x7e007e00`	RW	32	`0xf0ff017f`	`0000000000`
`DMA14_CONBLK_AD`	`0x7e007e04`	RW	32	`0xffffffe0`	`0000000000`
`DMA14_TI`	`0x7e007e08`	RO	26	`0x03fffff9`
`DMA14_SOURCE_AD`	`0x7e007e0c`	RO	32	`0xffffffff`
`DMA14_DEST_AD`	`0x7e007e10`	RO	32	`0xffffffff`
`DMA14_TXFR_LEN`	`0x7e007e14`	RO	16	`0x0000ffff`
`DMA14_NEXTCONBK`	`0x7e007e1c`	RO	32	`0xffffffe0`
`DMA14_DEBUG`	`0x7e007e20`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA14_CS

Info

Name	value	description
address	`0x7e007e00`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA14_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA14_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA14_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA14_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA14_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA14_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA14_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA14_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA14_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA14_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA14_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA14_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA14_CONBLK_AD

Info

Name	value	description
address	`0x7e007e04`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA14_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA14_TI

Info

Name	value	description
address	`0x7e007e08`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA14_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA14_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA14_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA14_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA14_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA14_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA14_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA14_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA14_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA14_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA14_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA14_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA14_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA14_SOURCE_AD

Info

Name	value	description
address	`0x7e007e0c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA14_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA14_DEST_AD

Info

Name	value	description
address	`0x7e007e10`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA14_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA14_TXFR_LEN

Info

Name	value	description
address	`0x7e007e14`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA14_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA14_NEXTCONBK

Info

Name	value	description
address	`0x7e007e1c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA14_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA14_DEBUG

Info

Name	value	description
address	`0x7e007e20`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA14_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA14_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA14_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA14_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA14_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA14_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA14_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA14_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA15

Description

TODO

Info

Name	value	description
base	`0x7ee05000`

Registers

name	address	type	width	mask	reset
`DMA15_CS`	`0x7ee05000`	RW	32	`0xf0ff017f`	`0000000000`
`DMA15_CONBLK_AD`	`0x7ee05004`	RW	32	`0xffffffe0`	`0000000000`
`DMA15_TI`	`0x7ee05008`	RO	27	`0x07fffffb`
`DMA15_SOURCE_AD`	`0x7ee0500c`	RO	32	`0xffffffff`
`DMA15_DEST_AD`	`0x7ee05010`	RO	32	`0xffffffff`
`DMA15_TXFR_LEN`	`0x7ee05014`	RO	30	`0x3fffffff`
`DMA15_STRIDE`	`0x7ee05018`	RO	32	`0xffffffff`
`DMA15_NEXTCONBK`	`0x7ee0501c`	RO	32	`0xffffffe0`
`DMA15_DEBUG`	`0x7ee05020`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA15_CS

Info

Name	value	description
address	`0x7ee05000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA15_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA15_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA15_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA15_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA15_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA15_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA15_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA15_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA15_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA15_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA15_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA15_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA15_CONBLK_AD

Info

Name	value	description
address	`0x7ee05004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA15_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA15_TI

Info

Name	value	description
address	`0x7ee05008`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA15_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA15_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA15_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA15_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA15_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA15_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA15_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA15_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA15_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA15_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA15_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA15_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA15_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA15_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA15_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA15_SOURCE_AD

Info

Name	value	description
address	`0x7ee0500c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA15_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA15_DEST_AD

Info

Name	value	description
address	`0x7ee05010`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA15_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA15_TXFR_LEN

Info

Name	value	description
address	`0x7ee05014`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA15_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA15_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA15_STRIDE

Info

Name	value	description
address	`0x7ee05018`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA15_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA15_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA15_NEXTCONBK

Info

Name	value	description
address	`0x7ee0501c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA15_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA15_DEBUG

Info

Name	value	description
address	`0x7ee05020`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA15_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA15_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA15_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA15_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA15_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA15_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA15_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA15_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA2

Description

TODO

Info

Name	value	description
base	`0x7e007200`

Registers

name	address	type	width	mask	reset
`DMA2_CS`	`0x7e007200`	RW	32	`0xf0ff017f`	`0000000000`
`DMA2_CONBLK_AD`	`0x7e007204`	RW	32	`0xffffffe0`	`0000000000`
`DMA2_TI`	`0x7e007208`	RO	27	`0x07fffffb`
`DMA2_SOURCE_AD`	`0x7e00720c`	RO	32	`0xffffffff`
`DMA2_DEST_AD`	`0x7e007210`	RO	32	`0xffffffff`
`DMA2_TXFR_LEN`	`0x7e007214`	RO	30	`0x3fffffff`
`DMA2_STRIDE`	`0x7e007218`	RO	32	`0xffffffff`
`DMA2_NEXTCONBK`	`0x7e00721c`	RO	32	`0xffffffe0`
`DMA2_DEBUG`	`0x7e007220`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA2_CS

Info

Name	value	description
address	`0x7e007200`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA2_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA2_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA2_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA2_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA2_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA2_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA2_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA2_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA2_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA2_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA2_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA2_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA2_CONBLK_AD

Info

Name	value	description
address	`0x7e007204`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA2_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA2_TI

Info

Name	value	description
address	`0x7e007208`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA2_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA2_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA2_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA2_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA2_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA2_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA2_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA2_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA2_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA2_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA2_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA2_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA2_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA2_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA2_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA2_SOURCE_AD

Info

Name	value	description
address	`0x7e00720c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA2_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA2_DEST_AD

Info

Name	value	description
address	`0x7e007210`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA2_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA2_TXFR_LEN

Info

Name	value	description
address	`0x7e007214`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA2_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA2_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA2_STRIDE

Info

Name	value	description
address	`0x7e007218`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA2_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA2_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA2_NEXTCONBK

Info

Name	value	description
address	`0x7e00721c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA2_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA2_DEBUG

Info

Name	value	description
address	`0x7e007220`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA2_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA2_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA2_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA2_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA2_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA2_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA2_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA2_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA3

Description

TODO

Info

Name	value	description
base	`0x7e007300`

Registers

name	address	type	width	mask	reset
`DMA3_CS`	`0x7e007300`	RW	32	`0xf0ff017f`	`0000000000`
`DMA3_CONBLK_AD`	`0x7e007304`	RW	32	`0xffffffe0`	`0000000000`
`DMA3_TI`	`0x7e007308`	RO	27	`0x07fffffb`
`DMA3_SOURCE_AD`	`0x7e00730c`	RO	32	`0xffffffff`
`DMA3_DEST_AD`	`0x7e007310`	RO	32	`0xffffffff`
`DMA3_TXFR_LEN`	`0x7e007314`	RO	30	`0x3fffffff`
`DMA3_STRIDE`	`0x7e007318`	RO	32	`0xffffffff`
`DMA3_NEXTCONBK`	`0x7e00731c`	RO	32	`0xffffffe0`
`DMA3_DEBUG`	`0x7e007320`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA3_CS

Info

Name	value	description
address	`0x7e007300`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA3_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA3_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA3_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA3_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA3_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA3_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA3_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA3_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA3_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA3_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA3_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA3_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA3_CONBLK_AD

Info

Name	value	description
address	`0x7e007304`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA3_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA3_TI

Info

Name	value	description
address	`0x7e007308`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA3_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA3_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA3_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA3_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA3_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA3_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA3_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA3_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA3_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA3_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA3_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA3_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA3_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA3_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA3_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA3_SOURCE_AD

Info

Name	value	description
address	`0x7e00730c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA3_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA3_DEST_AD

Info

Name	value	description
address	`0x7e007310`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA3_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA3_TXFR_LEN

Info

Name	value	description
address	`0x7e007314`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA3_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA3_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA3_STRIDE

Info

Name	value	description
address	`0x7e007318`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA3_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA3_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA3_NEXTCONBK

Info

Name	value	description
address	`0x7e00731c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA3_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA3_DEBUG

Info

Name	value	description
address	`0x7e007320`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA3_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA3_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA3_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA3_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA3_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA3_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA3_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA3_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA4

Description

TODO

Info

Name	value	description
base	`0x7e007400`

Registers

name	address	type	width	mask	reset
`DMA4_CS`	`0x7e007400`	RW	32	`0xf0ff017f`	`0000000000`
`DMA4_CONBLK_AD`	`0x7e007404`	RW	32	`0xffffffe0`	`0000000000`
`DMA4_TI`	`0x7e007408`	RO	27	`0x07fffffb`
`DMA4_SOURCE_AD`	`0x7e00740c`	RO	32	`0xffffffff`
`DMA4_DEST_AD`	`0x7e007410`	RO	32	`0xffffffff`
`DMA4_TXFR_LEN`	`0x7e007414`	RO	30	`0x3fffffff`
`DMA4_STRIDE`	`0x7e007418`	RO	32	`0xffffffff`
`DMA4_NEXTCONBK`	`0x7e00741c`	RO	32	`0xffffffe0`
`DMA4_DEBUG`	`0x7e007420`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA4_CS

Info

Name	value	description
address	`0x7e007400`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA4_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA4_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA4_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA4_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA4_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA4_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA4_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA4_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA4_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA4_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA4_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA4_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA4_CONBLK_AD

Info

Name	value	description
address	`0x7e007404`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA4_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA4_TI

Info

Name	value	description
address	`0x7e007408`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA4_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA4_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA4_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA4_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA4_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA4_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA4_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA4_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA4_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA4_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA4_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA4_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA4_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA4_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA4_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA4_SOURCE_AD

Info

Name	value	description
address	`0x7e00740c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA4_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA4_DEST_AD

Info

Name	value	description
address	`0x7e007410`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA4_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA4_TXFR_LEN

Info

Name	value	description
address	`0x7e007414`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA4_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA4_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA4_STRIDE

Info

Name	value	description
address	`0x7e007418`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA4_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA4_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA4_NEXTCONBK

Info

Name	value	description
address	`0x7e00741c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA4_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA4_DEBUG

Info

Name	value	description
address	`0x7e007420`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA4_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA4_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA4_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA4_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA4_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA4_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA4_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA4_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA5

Description

TODO

Info

Name	value	description
base	`0x7e007500`

Registers

name	address	type	width	mask	reset
`DMA5_CS`	`0x7e007500`	RW	32	`0xf0ff017f`	`0000000000`
`DMA5_CONBLK_AD`	`0x7e007504`	RW	32	`0xffffffe0`	`0000000000`
`DMA5_TI`	`0x7e007508`	RO	27	`0x07fffffb`
`DMA5_SOURCE_AD`	`0x7e00750c`	RO	32	`0xffffffff`
`DMA5_DEST_AD`	`0x7e007510`	RO	32	`0xffffffff`
`DMA5_TXFR_LEN`	`0x7e007514`	RO	30	`0x3fffffff`
`DMA5_STRIDE`	`0x7e007518`	RO	32	`0xffffffff`
`DMA5_NEXTCONBK`	`0x7e00751c`	RO	32	`0xffffffe0`
`DMA5_DEBUG`	`0x7e007520`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA5_CS

Info

Name	value	description
address	`0x7e007500`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA5_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA5_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA5_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA5_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA5_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA5_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA5_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA5_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA5_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA5_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA5_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA5_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA5_CONBLK_AD

Info

Name	value	description
address	`0x7e007504`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA5_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA5_TI

Info

Name	value	description
address	`0x7e007508`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA5_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA5_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA5_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA5_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA5_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA5_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA5_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA5_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA5_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA5_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA5_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA5_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA5_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA5_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA5_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA5_SOURCE_AD

Info

Name	value	description
address	`0x7e00750c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA5_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA5_DEST_AD

Info

Name	value	description
address	`0x7e007510`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA5_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA5_TXFR_LEN

Info

Name	value	description
address	`0x7e007514`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA5_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA5_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA5_STRIDE

Info

Name	value	description
address	`0x7e007518`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA5_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA5_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA5_NEXTCONBK

Info

Name	value	description
address	`0x7e00751c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA5_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA5_DEBUG

Info

Name	value	description
address	`0x7e007520`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA5_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA5_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA5_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA5_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA5_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA5_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA5_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA5_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA6

Description

TODO

Info

Name	value	description
base	`0x7e007600`

Registers

name	address	type	width	mask	reset
`DMA6_CS`	`0x7e007600`	RW	32	`0xf0ff017f`	`0000000000`
`DMA6_CONBLK_AD`	`0x7e007604`	RW	32	`0xffffffe0`	`0000000000`
`DMA6_TI`	`0x7e007608`	RO	27	`0x07fffffb`
`DMA6_SOURCE_AD`	`0x7e00760c`	RO	32	`0xffffffff`
`DMA6_DEST_AD`	`0x7e007610`	RO	32	`0xffffffff`
`DMA6_TXFR_LEN`	`0x7e007614`	RO	30	`0x3fffffff`
`DMA6_STRIDE`	`0x7e007618`	RO	32	`0xffffffff`
`DMA6_NEXTCONBK`	`0x7e00761c`	RO	32	`0xffffffe0`
`DMA6_DEBUG`	`0x7e007620`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA6_CS

Info

Name	value	description
address	`0x7e007600`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA6_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA6_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA6_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA6_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA6_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA6_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA6_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA6_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA6_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA6_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA6_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA6_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA6_CONBLK_AD

Info

Name	value	description
address	`0x7e007604`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA6_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA6_TI

Info

Name	value	description
address	`0x7e007608`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA6_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`DMA6_TI_TDMODE`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	2	2	`NA`	`NA`	`NA`
`DMA6_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA6_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA6_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA6_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA6_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA6_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA6_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA6_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA6_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA6_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA6_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA6_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`
`DMA6_TI_NO_WIDE_BURSTS`	26	26	`0x04000000`	`0xfbffffff`

DMA6_SOURCE_AD

Info

Name	value	description
address	`0x7e00760c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA6_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA6_DEST_AD

Info

Name	value	description
address	`0x7e007610`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA6_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA6_TXFR_LEN

Info

Name	value	description
address	`0x7e007614`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA6_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`
`DMA6_TXFR_LEN_YLENGTH`	16	29	`0x3fff0000`	`0xc000ffff`

DMA6_STRIDE

Info

Name	value	description
address	`0x7e007618`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA6_STRIDE_S_STRIDE`	0	15	`0x0000ffff`	`0xffff0000`
`DMA6_STRIDE_D_STRIDE`	16	31	`0xffff0000`	`0x0000ffff`

DMA6_NEXTCONBK

Info

Name	value	description
address	`0x7e00761c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA6_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA6_DEBUG

Info

Name	value	description
address	`0x7e007620`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA6_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA6_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA6_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA6_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA6_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA6_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA6_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA6_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA7

Description

TODO

Info

Name	value	description
base	`0x7e007700`

Registers

name	address	type	width	mask	reset
`DMA7_CS`	`0x7e007700`	RW	32	`0xf0ff017f`	`0000000000`
`DMA7_CONBLK_AD`	`0x7e007704`	RW	32	`0xffffffe0`	`0000000000`
`DMA7_TI`	`0x7e007708`	RO	26	`0x03fffff9`
`DMA7_SOURCE_AD`	`0x7e00770c`	RO	32	`0xffffffff`
`DMA7_DEST_AD`	`0x7e007710`	RO	32	`0xffffffff`
`DMA7_TXFR_LEN`	`0x7e007714`	RO	16	`0x0000ffff`
`DMA7_NEXTCONBK`	`0x7e00771c`	RO	32	`0xffffffe0`
`DMA7_DEBUG`	`0x7e007720`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA7_CS

Info

Name	value	description
address	`0x7e007700`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA7_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA7_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA7_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA7_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA7_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA7_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA7_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA7_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA7_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA7_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA7_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA7_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA7_CONBLK_AD

Info

Name	value	description
address	`0x7e007704`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA7_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA7_TI

Info

Name	value	description
address	`0x7e007708`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA7_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA7_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA7_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA7_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA7_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA7_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA7_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA7_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA7_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA7_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA7_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA7_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA7_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA7_SOURCE_AD

Info

Name	value	description
address	`0x7e00770c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA7_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA7_DEST_AD

Info

Name	value	description
address	`0x7e007710`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA7_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA7_TXFR_LEN

Info

Name	value	description
address	`0x7e007714`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA7_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA7_NEXTCONBK

Info

Name	value	description
address	`0x7e00771c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA7_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA7_DEBUG

Info

Name	value	description
address	`0x7e007720`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA7_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA7_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA7_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA7_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA7_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA7_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA7_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA7_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA8

Description

TODO

Info

Name	value	description
base	`0x7e007800`

Registers

name	address	type	width	mask	reset
`DMA8_CS`	`0x7e007800`	RW	32	`0xf0ff017f`	`0000000000`
`DMA8_CONBLK_AD`	`0x7e007804`	RW	32	`0xffffffe0`	`0000000000`
`DMA8_TI`	`0x7e007808`	RO	26	`0x03fffff9`
`DMA8_SOURCE_AD`	`0x7e00780c`	RO	32	`0xffffffff`
`DMA8_DEST_AD`	`0x7e007810`	RO	32	`0xffffffff`
`DMA8_TXFR_LEN`	`0x7e007814`	RO	16	`0x0000ffff`
`DMA8_NEXTCONBK`	`0x7e00781c`	RO	32	`0xffffffe0`
`DMA8_DEBUG`	`0x7e007820`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA8_CS

Info

Name	value	description
address	`0x7e007800`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA8_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA8_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA8_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA8_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA8_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA8_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA8_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA8_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA8_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA8_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA8_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA8_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA8_CONBLK_AD

Info

Name	value	description
address	`0x7e007804`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA8_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA8_TI

Info

Name	value	description
address	`0x7e007808`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA8_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA8_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA8_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA8_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA8_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA8_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA8_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA8_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA8_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA8_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA8_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA8_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA8_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA8_SOURCE_AD

Info

Name	value	description
address	`0x7e00780c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA8_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA8_DEST_AD

Info

Name	value	description
address	`0x7e007810`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA8_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA8_TXFR_LEN

Info

Name	value	description
address	`0x7e007814`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA8_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA8_NEXTCONBK

Info

Name	value	description
address	`0x7e00781c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA8_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA8_DEBUG

Info

Name	value	description
address	`0x7e007820`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA8_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA8_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA8_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA8_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA8_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA8_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA8_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA8_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DMA9

Description

TODO

Info

Name	value	description
base	`0x7e007900`

Registers

name	address	type	width	mask	reset
`DMA9_CS`	`0x7e007900`	RW	32	`0xf0ff017f`	`0000000000`
`DMA9_CONBLK_AD`	`0x7e007904`	RW	32	`0xffffffe0`	`0000000000`
`DMA9_TI`	`0x7e007908`	RO	26	`0x03fffff9`
`DMA9_SOURCE_AD`	`0x7e00790c`	RO	32	`0xffffffff`
`DMA9_DEST_AD`	`0x7e007910`	RO	32	`0xffffffff`
`DMA9_TXFR_LEN`	`0x7e007914`	RO	16	`0x0000ffff`
`DMA9_NEXTCONBK`	`0x7e00791c`	RO	32	`0xffffffe0`
`DMA9_DEBUG`	`0x7e007920`	RW	29	`0x1ffffff7`	`0000000000`

Register details

DMA9_CS

Info

Name	value	description
address	`0x7e007900`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA9_CS_ACTIVE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA9_CS_END`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA9_CS_INT`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`DMA9_CS_DREQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`DMA9_CS_PAUSED`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DMA9_CS_DREQ_STOPS_DMA`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DMA9_CS_ERROR`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`missing definiton`	9	15	`NA`	`NA`	`NA`
`DMA9_CS_PRIORITY`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`DMA9_CS_PANIC_PRIORITY`	20	23	`0x00f00000`	`0xff0fffff`	`0x0`
`missing definiton`	24	27	`NA`	`NA`	`NA`
`DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`DMA9_CS_DISDEBUG`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`DMA9_CS_ABORT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`DMA9_CS_RESET`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

DMA9_CONBLK_AD

Info

Name	value	description
address	`0x7e007904`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA9_CONBLK_AD_SCB_ADDR`	5	31	`0xffffffe0`	`0x0000001f`	`0x0`

DMA9_TI

Info

Name	value	description
address	`0x7e007908`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA9_TI_INTEN`	0	0	`0x00000001`	`0xfffffffe`
`missing definiton`	1	2	`NA`	`NA`	`NA`
`DMA9_TI_WAIT_RESP`	3	3	`0x00000008`	`0xfffffff7`
`DMA9_TI_DEST_INC`	4	4	`0x00000010`	`0xffffffef`
`DMA9_TI_DEST_WIDTH`	5	5	`0x00000020`	`0xffffffdf`
`DMA9_TI_DEST_DREQ`	6	6	`0x00000040`	`0xffffffbf`
`DMA9_TI_DEST_IGNORE`	7	7	`0x00000080`	`0xffffff7f`
`DMA9_TI_SRC_INC`	8	8	`0x00000100`	`0xfffffeff`
`DMA9_TI_SRC_WIDTH`	9	9	`0x00000200`	`0xfffffdff`
`DMA9_TI_SRC_DREQ`	10	10	`0x00000400`	`0xfffffbff`
`DMA9_TI_SRC_IGNORE`	11	11	`0x00000800`	`0xfffff7ff`
`DMA9_TI_BURST_LENGTH`	12	15	`0x0000f000`	`0xffff0fff`
`DMA9_TI_PERMAP`	16	20	`0x001f0000`	`0xffe0ffff`
`DMA9_TI_WAITS`	21	25	`0x03e00000`	`0xfc1fffff`

DMA9_SOURCE_AD

Info

Name	value	description
address	`0x7e00790c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA9_SOURCE_AD_S_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA9_DEST_AD

Info

Name	value	description
address	`0x7e007910`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA9_DEST_AD_D_ADDR`	0	31	`0xffffffff`	`0x00000000`

DMA9_TXFR_LEN

Info

Name	value	description
address	`0x7e007914`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`DMA9_TXFR_LEN_XLENGTH`	0	15	`0x0000ffff`	`0xffff0000`

DMA9_NEXTCONBK

Info

Name	value	description
address	`0x7e00791c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`missing definiton`	0	4	`NA`	`NA`	`NA`
`DMA9_NEXTCONBK_ADDR`	5	31	`0xffffffe0`	`0x0000001f`

DMA9_DEBUG

Info

Name	value	description
address	`0x7e007920`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DMA9_DEBUG_READ_LAST_NOT_SET_ERROR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DMA9_DEBUG_FIFO_ERROR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DMA9_DEBUG_READ_ERROR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DMA9_DEBUG_OUTSTANDING_WRITES`	4	7	`0x000000f0`	`0xffffff0f`	`0x0`
`DMA9_DEBUG_DMA_ID`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`DMA9_DEBUG_DMA_STATE`	16	24	`0x01ff0000`	`0xfe00ffff`	`0x0`
`DMA9_DEBUG_VERSION`	25	27	`0x0e000000`	`0xf1ffffff`	`0x0`
`DMA9_DEBUG_LITE`	28	28	`0x10000000`	`0xefffffff`	`0x0`

DPHY_CSR

Description

TODO

Info

Name	value	description
base	`0x7ee07000`

Registers

name	address	type	width	mask	reset
`DPHY_CSR_DQ_REV_ID`	`0x7ee07000`	RW
`DPHY_CSR_GLBL_DQ_DLL_RESET`	`0x7ee07004`	RW
`DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE`	`0x7ee07008`	RW
`DPHY_CSR_GLBL_DQ_DLL_CNTRL`	`0x7ee0700c`	RW
`DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL`	`0x7ee07010`	RW
`DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN`	`0x7ee07014`	RW
`DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT`	`0x7ee07018`	RW
`DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET`	`0x7ee0701c`	RW
`DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET`	`0x7ee07020`	RW
`DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET`	`0x7ee07024`	RW
`DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET`	`0x7ee07028`	RW
`DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT`	`0x7ee0702c`	RW
`DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT`	`0x7ee07030`	RW
`DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT`	`0x7ee07034`	RW
`DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT`	`0x7ee07038`	RW
`DPHY_CSR_NORM_READ_DQS_GATE_CTRL`	`0x7ee0703c`	RW
`DPHY_CSR_BOOT_READ_DQS_GATE_CTRL`	`0x7ee07040`	RW
`DPHY_CSR_PHY_FIFO_PNTRS`	`0x7ee07044`	RW
`DPHY_CSR_DQ_PHY_MISC_CTRL`	`0x7ee07048`	RW
`DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL`	`0x7ee0704c`	RW
`DPHY_CSR_DQ_PAD_MISC_CTRL`	`0x7ee07050`	RW
`DPHY_CSR_DQ_PVT_COMP_CTRL`	`0x7ee07054`	RW
`DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL`	`0x7ee07058`	RW
`DPHY_CSR_DQ_PVT_COMP_STATUS`	`0x7ee0705c`	RW
`DPHY_CSR_DQ_PVT_COMP_DEBUG`	`0x7ee07060`	RW
`DPHY_CSR_DQ_PHY_READ_CTRL`	`0x7ee07064`	RW
`DPHY_CSR_DQ_PHY_READ_STATUS`	`0x7ee07068`	RW
`DPHY_CSR_DQ_SPR_RW`	`0x7ee0706c`	RW
`DPHY_CSR_DQ_SPR1_RO`	`0x7ee07070`	RW
`DPHY_CSR_DQ_SPR_RO`	`0x7ee07074`	RW
`DPHY_CSR_CRC_CTRL`	`0x7ee07800`	RW	9	`0x00000111`	`0000000000`
`DPHY_CSR_CRC_DATA`	`0x7ee07804`	RW	28	`0x0fffffff`	`0000000000`

Register details

DPI

Description

TODO

Info

Name	value	description
base	`0x7e208000`
id	`0x44504920`

unknown defined macro

define	type	description
`DPI_DPIC`	UNKNOWN

Registers

name	address	type	width	mask	reset	description
`DPI_C`	`0x7e208000`	RW	16	`0x0000ffff`	`0x00003000`

Register details

DSI0

Description

TODO

Info

Name	value	description
base	`0x7e209000`
id	`0x00647369`

Registers

name	address	type	width	mask	reset
`DSI0_CTRL`	`0x7e209000`	RW	3	`0x00000007`	`0000000000`
`DSI0_CMD_PKTC`	`0x7e209004`	RW	32	`0xffffffff`	`0000000000`
`DSI0_CMD_PKTH`	`0x7e209008`	RW	32	`0xffffffff`	`0000000000`
`DSI0_RX1_PKTH`	`0x7e20900c`	RO	32	`0xffffffff`
`DSI0_RX2_PKTH`	`0x7e209010`	RO	32	`0xffffffff`
`DSI0_CMD_DATAF`	`0x7e209014`	RW	8	`0x000000ff`
`DSI0_DISP0_CTR`	`0x7e209018`	RW	32	`0xffffffff`	`0000000000`
`DSI0_DISP1_CTR`	`0x7e20901c`	RW	32	`0xffffffff`	`0000000000`
`DSI0_PIX_FIFO`	`0x7e209020`	RW	32	`0xffffffff`
`DSI0_INT_STAT`	`0x7e209024`	RW	32	`0xffffffff`
`DSI0_INT_EN`	`0x7e209028`	RW	28	`0x0fffffff`	`0000000000`
`DSI0_STAT`	`0x7e20902c`	RW	32	`0xffffffff`
`DSI0_HSTX_TO_C`	`0x7e209030`	RW	24	`0x00ffffff`	`0000000000`
`DSI0_LPRX_TO_C`	`0x7e209034`	RW	32	`0xffffffff`	`0000000000`
`DSI0_TA_TO_CNT`	`0x7e209038`	RW	32	`0xffffffff`	`0000000000`
`DSI0_PR_TO_CNT`	`0x7e20903c`	RW	32	`0xffffffff`	`0000000000`
`DSI0_PHYC`	`0x7e209040`	RW	18	`0x0003f777`	`0000000000`
`DSI0_HS_CLT0`	`0x7e209044`	RW	32	`0xfffffffc`	`0000000000`
`DSI0_HS_CLT1`	`0x7e209048`	RW	10	`0x000003fc`	`0000000000`
`DSI0_HS_CLT2`	`0x7e20904c`	RW	10	`0x000003fc`	`0000000000`
`DSI0_HS_DLT3`	`0x7e209050`	RW	10	`0x000003fc`	`0000000000`
`DSI0_HS_DLT4`	`0x7e209054`	RW	10	`0x000003fc`	`0000000000`
`DSI0_HS_DLT5`	`0x7e209058`	RW	10	`0x000003fc`	`0000000000`
`DSI0_LP_DLT6`	`0x7e20905c`	RW	10	`0x000003fc`	`0000000000`
`DSI0_LP_DLT7`	`0x7e209060`	RW	10	`0x000003fc`	`0000000000`
`DSI0_PHY_AFEC0`	`0x7e209064`	RW	8	`0x000000ff`	`0000000000`
`DSI0_PHY_AFEC1`	`0x7e209068`	RW	32	`0xffffffff`	`0000000000`
`DSI0_TST_SEL`	`0x7e20906c`	RW	8	`0x000000ff`	`0000000000`
`DSI0_TST_MON`	`0x7e209070`	RW	8	`0x000000ff`	`0000000000`

Register details

DSI0_CTRL

Info

Name	value	description
address	`0x7e209000`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DSI0_CTRL_CTRL0`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DSI0_CTRL_CTRL1`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DSI0_CTRL_CTRL2`	2	2	`0x00000004`	`0xfffffffb`	`0x0`

DSI0_PHYC

Info

Name	value	description
address	`0x7e209040`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`DSI0_PHYC_dlane_hsen_0_sync`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`DSI0_PHYC_txulpshs_0_sync`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`DSI0_PHYC_forcehsstop_sync`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`DSI0_PHYC_unused`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`DSI0_PHYC_dlane_hsen_1_sync`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`DSI0_PHYC_txulpshs_1_sync`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`DSI0_PHYC_clane_hsen_sync`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`DSI0_PHYC_txulps_clk_sync`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`DSI0_PHYC_txhsclk_cont_sync`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`missing definiton`	11	11	`NA`	`NA`	`NA`
`DSI0_PHYC_dsi_esc_lpdt`	12	17	`0x0003f000`	`0xfffc0fff`	`0x0`

DSI1

Description

TODO

Info

Name	value	description
base	`0x7e700000`
id	`0x64736934`

Registers

name	address	type	width	mask	reset
`DSI1_CTRL`	`0x7e700000`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TXPKT1_C`	`0x7e700004`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TXPKT1_H`	`0x7e700008`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TXPKT2_C`	`0x7e70000c`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TXPKT2_H`	`0x7e700010`	RW	32	`0xffffffff`	`0000000000`
`DSI1_RXPKT1_H`	`0x7e700014`	RO	32	`0xffffffff`
`DSI1_RXPKT2_H`	`0x7e700018`	RO	32	`0xffffffff`
`DSI1_TXPKT_CMD_FIFO`	`0x7e70001c`	RW	8	`0x000000ff`
`DSI1_TXPKT_PIXD_FIFO`	`0x7e700020`	RW	32	`0xffffffff`	`0000000000`
`DSI1_RXPKT_FIFO`	`0x7e700024`	RW	32	`0xffffffff`	`0000000000`
`DSI1_DISP0_CTRL`	`0x7e700028`	RW	32	`0xffffffff`
`DSI1_DISP1_CTRL`	`0x7e70002c`	RW	32	`0xffffffff`
`DSI1_INT_STAT`	`0x7e700030`	RW	32	`0xffffffff`
`DSI1_INT_EN`	`0x7e700034`	RW	28	`0x0fffffff`	`0000000000`
`DSI1_STAT`	`0x7e700038`	RW	32	`0xffffffff`
`DSI1_HSTX_TO_CNT`	`0x7e70003c`	RW	24	`0x00ffffff`	`0000000000`
`DSI1_LPRX_TO_CNT`	`0x7e700040`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TA_TO_CNT`	`0x7e700044`	RW	32	`0xffffffff`	`0000000000`
`DSI1_PR_TO_CNT`	`0x7e700048`	RW	32	`0xffffffff`	`0000000000`
`DSI1_PHYC`	`0x7e70004c`	RW	32	`0xffffffff`	`0000000000`
`DSI1_HS_CLT0`	`0x7e700050`	RW	32	`0xffffffff`	`0000000000`
`DSI1_HS_CLT1`	`0x7e700054`	RW	32	`0xffffffff`	`0000000000`
`DSI1_HS_CLT2`	`0x7e700058`	RW	32	`0xffffffff`	`0000000000`
`DSI1_HS_DLT3`	`0x7e70005c`	RW	32	`0xffffffff`	`0000000000`
`DSI1_HS_DLT4`	`0x7e700060`	RW	32	`0xffffffff`	`0000000000`
`DSI1_HS_DLT5`	`0x7e700064`	RW	32	`0xffffffff`	`0000000000`
`DSI1_LP_DLT6`	`0x7e700068`	RW	32	`0xffffffff`	`0000000000`
`DSI1_LP_DLT7`	`0x7e70006c`	RW	32	`0xffffffff`	`0000000000`
`DSI1_PHY_AFEC0`	`0x7e700070`	RW	32	`0xffffffff`	`0000000000`
`DSI1_PHY_AFEC1`	`0x7e700074`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TST_SEL`	`0x7e700078`	RW	32	`0xffffffff`	`0000000000`
`DSI1_TST_MON`	`0x7e70007c`	RW	32	`0xffffffff`	`0000000000`

Register details

EMMC

Description

TODO

Info

Name	value	description
base	`0x7e300000`

Registers

name	address	type	width	mask	reset
`EMMC_ARG2`	`0x7e300000`	RW	32	`0xffffffff`	`0000000000`
`EMMC_BLKSIZECNT`	`0x7e300004`	RW	32	`0xffffffff`	`0000000000`
`EMMC_ARG1`	`0x7e300008`	RW	32	`0xffffffff`	`0000000000`
`EMMC_CMDTM`	`0x7e30000c`	RW	30	`0x3ffb003f`	`0000000000`
`EMMC_RESP0`	`0x7e300010`	RW	32	`0xffffffff`	`0000000000`
`EMMC_RESP1`	`0x7e300014`	RW	32	`0xffffffff`	`0000000000`
`EMMC_RESP2`	`0x7e300018`	RW	32	`0xffffffff`	`0000000000`
`EMMC_RESP3`	`0x7e30001c`	RW	32	`0xffffffff`	`0000000000`
`EMMC_DATA`	`0x7e300020`	RW	32	`0xffffffff`	`0000000000`
`EMMC_STATUS`	`0x7e300024`	RW	29	`0x1fff0f0f`	`0x1ff00000`
`EMMC_CONTROL0`	`0x7e300028`	RW	27	`0x07ff1fff`	`0000000000`
`EMMC_CONTROL1`	`0x7e30002c`	RW	27	`0x070fffe7`	`0000000000`
`EMMC_INTERRUPT`	`0x7e300030`	RW	32	`0xffffffff`	`0000000000`
`EMMC_IRPT_MASK`	`0x7e300034`	RW	32	`0xffffffff`	`0000000000`
`EMMC_IRPT_EN`	`0x7e300038`	RW	32	`0xffffffff`	`0000000000`
`EMMC_CONTROL2`	`0x7e30003c`	RW	32	`0xc0ff009f`	`0x00080000`
`EMMC_HWCAP0`	`0x7e300040`	RW	32	`0xffffffff`	`0000000000`
`EMMC_HWCAP1`	`0x7e300044`	RW	26	`0x03ffef77`	`0x03000777`
`EMMC_HWMAXAMP0`	`0x7e300048`	RW	24	`0x00ffffff`	`0000000000`
`EMMC_FORCE_IRPT`	`0x7e300050`	RW	32	`0xffff00ff`	`0x00000001`
`EMMC_DMA_STATUS`	`0x7e300054`	RW	32	`0xffff00ff`	`0000000000`
`EMMC_BOOT_TIMEOUT`	`0x7e300070`	RW	32	`0xffffffff`	`0000000000`
`EMMC_DBG_SEL`	`0x7e300074`	RW	1	`0x00000001`	`0000000000`
`EMMC_EXRDFIFO_CFG`	`0x7e300080`	RW	3	`0x00000007`	`0000000000`
`EMMC_EXRDFIFO_EN`	`0x7e300084`	RW	1	`0x00000001`	`0000000000`
`EMMC_TUNE_STEP`	`0x7e300088`	RW	3	`0x00000007`	`0000000000`
`EMMC_TUNE_STEPS_STD`	`0x7e30008c`	RW	6	`0x0000003f`	`0000000000`
`EMMC_TUNE_STEPS_DDR`	`0x7e300090`	RW	6	`0x0000003f`	`0000000000`
`EMMC_BUS_CTRL`	`0x7e3000e0`	RW	32	`0xffffffff`	`0000000000`
`EMMC_SPI_INT_SPT`	`0x7e3000f0`	RW	8	`0x000000ff`	`0000000000`
`EMMC_SLOTISR_VER`	`0x7e3000fc`	RW	32	`0xffff00ff`	`0x99020000`

Register details

EMMC_BLKSIZECNT

Info

Name	value	description
address	`0x7e300004`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_BLKSIZECNT_BLKSIZE`	0	11	`0x00000fff`	`0xfffff000`	`0x0`
`EMMC_BLKSIZECNT_SDMA_BLKSIZE`	12	14	`0x00007000`	`0xffff8fff`	`0x0`
`EMMC_BLKSIZECNT_BLKSIZE_MS1`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`EMMC_BLKSIZECNT_BLKCNT`	16	31	`0xffff0000`	`0x0000ffff`	`0x0`

EMMC_CMDTM

Info

Name	value	description
address	`0x7e30000c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_CMDTM_TM_DMA_EN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_CMDTM_TM_BLKCNT_EN`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_CMDTM_TM_AUTO_CMD_EN`	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
`EMMC_CMDTM_TM_DAT_DIR`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`EMMC_CMDTM_TM_MULTI_BLOCK`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`missing definiton`	6	15	`NA`	`NA`	`NA`
`EMMC_CMDTM_CMD_RSPNS_TYPE`	16	17	`0x00030000`	`0xfffcffff`	`0x0`
`missing definiton`	18	18	`NA`	`NA`	`NA`
`EMMC_CMDTM_CMD_CRCCHK_EN`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_CMDTM_CMD_IXCHK_EN`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`EMMC_CMDTM_CMD_ISDATA`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_CMDTM_CMD_TYPE`	22	23	`0x00c00000`	`0xff3fffff`	`0x0`
`EMMC_CMDTM_CMD_INDEX`	24	29	`0x3f000000`	`0xc0ffffff`	`0x0`

EMMC_STATUS

Info

Name	value	description
address	`0x7e300024`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_STATUS_CMD_INHIBIT`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_STATUS_DAT_INHIBIT`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_STATUS_DAT_ACTIVE`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_STATUS_RETUNING_REQ`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`missing definiton`	4	7	`NA`	`NA`	`NA`
`EMMC_STATUS_WRITE_TRANSFER`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`EMMC_STATUS_READ_TRANSFER`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`EMMC_STATUS_NEW_WRITE_DATA`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`EMMC_STATUS_NEW_READ_DATA`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`missing definiton`	12	15	`NA`	`NA`	`NA`
`EMMC_STATUS_CARD_INSERT`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`EMMC_STATUS_CARD_STABLE`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`EMMC_STATUS_CARD_DETECT`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_STATUS_WRT_PROTECT`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_STATUS_DAT_LEVEL0`	20	23	`0x00f00000`	`0xff0fffff`	`0xf`
`EMMC_STATUS_CMD_LEVEL`	24	24	`0x01000000`	`0xfeffffff`	`0x1`
`EMMC_STATUS_DAT_LEVEL1`	25	28	`0x1e000000`	`0xe1ffffff`	`0xf`

EMMC_CONTROL0

Info

Name	value	description
address	`0x7e300028`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_CONTROL0_HCTL_LED`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_CONTROL0_HCTL_DWIDTH`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_CONTROL0_HCTL_HS_EN`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_CONTROL0_HCTL_DMA`	3	4	`0x00000018`	`0xffffffe7`	`0x0`
`EMMC_CONTROL0_HCTL_8BIT`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`EMMC_CONTROL0_HCTL_CRDDET`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`EMMC_CONTROL0_HCTL_CRDDET_S`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`EMMC_CONTROL0_PWCTL_ON`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`EMMC_CONTROL0_PWCTL_SDVOLTS`	9	11	`0x00000e00`	`0xfffff1ff`	`0x0`
`EMMC_CONTROL0_PWCTL_HWRST`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`missing definiton`	13	15	`NA`	`NA`	`NA`
`EMMC_CONTROL0_GAP_STOP`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`EMMC_CONTROL0_GAP_RESTART`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`EMMC_CONTROL0_READWAIT_EN`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_CONTROL0_GAP_IEN`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_CONTROL0_SPI_MODE`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`EMMC_CONTROL0_BOOT_EN`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_CONTROL0_ALT_BOOT_EN`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`missing definiton`	23	23	`NA`	`NA`	`NA`
`EMMC_CONTROL0_WAKE_ONINT_EN`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_CONTROL0_WAKE_ONINS_EN`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`EMMC_CONTROL0_WAKE_ONREM_EN`	26	26	`0x04000000`	`0xfbffffff`	`0x0`

EMMC_CONTROL1

Info

Name	value	description
address	`0x7e30002c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_CONTROL1_CLK_INTLEN`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_CONTROL1_CLK_STABLE`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_CONTROL1_CLK_EN`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`missing definiton`	3	4	`NA`	`NA`	`NA`
`EMMC_CONTROL1_CLK_GENSEL`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`EMMC_CONTROL1_CLK_FREQ_MS2`	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
`EMMC_CONTROL1_CLK_FREQ8`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`EMMC_CONTROL1_DATA_TOUNIT`	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
`missing definiton`	20	23	`NA`	`NA`	`NA`
`EMMC_CONTROL1_SRST_HC`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_CONTROL1_SRST_CMD`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`EMMC_CONTROL1_SRST_DATA`	26	26	`0x04000000`	`0xfbffffff`	`0x0`

EMMC_INTERRUPT

Info

Name	value	description
address	`0x7e300030`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_INTERRUPT_CMD_DONE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_INTERRUPT_DATA_DONE`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_INTERRUPT_BLOCK_GAP`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_INTERRUPT_DMA`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`EMMC_INTERRUPT_WRITE_RDY`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`EMMC_INTERRUPT_READ_RDY`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`EMMC_INTERRUPT_CARD_IN`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`EMMC_INTERRUPT_CARD_OUT`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`EMMC_INTERRUPT_CARD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`EMMC_INTERRUPT_INT_A`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`EMMC_INTERRUPT_INT_B`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`EMMC_INTERRUPT_INT_C`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`EMMC_INTERRUPT_RETUNE`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`EMMC_INTERRUPT_BOOTACK`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`EMMC_INTERRUPT_ENDBOOT`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`EMMC_INTERRUPT_ERR`	15	15	`0x00008000`	`0xffff7fff`	`0x0`
`EMMC_INTERRUPT_CTO_ERR`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`EMMC_INTERRUPT_CCRC_ERR`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`EMMC_INTERRUPT_CEND_ERR`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_INTERRUPT_CBAD_ERR`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_INTERRUPT_DTO_ERR`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`EMMC_INTERRUPT_DCRC_ERR`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_INTERRUPT_DEND_ERR`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`EMMC_INTERRUPT_SDOFF_ERR`	23	23	`0x00800000`	`0xff7fffff`	`0x0`
`EMMC_INTERRUPT_ACMD_ERR`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_INTERRUPT_ADMA_ERR`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`EMMC_INTERRUPT_TUNE_ERR`	26	26	`0x04000000`	`0xfbffffff`	`0x0`
`missing definiton`	27	27	`NA`	`NA`	`NA`
`EMMC_INTERRUPT_DMA_ERR`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`EMMC_INTERRUPT_ATA_ERR`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`EMMC_INTERRUPT_OEM_ERR`	30	31	`0xc0000000`	`0x3fffffff`	`0x0`

EMMC_IRPT_MASK

Info

Name	value	description
address	`0x7e300034`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_IRPT_MASK_CMD_DONE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_IRPT_MASK_DATA_DONE`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_IRPT_MASK_BLOCK_GAP`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_IRPT_MASK_DMA`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`EMMC_IRPT_MASK_WRITE_RDY`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`EMMC_IRPT_MASK_READ_RDY`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`EMMC_IRPT_MASK_CARD_IN`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`EMMC_IRPT_MASK_CARD_OUT`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`EMMC_IRPT_MASK_CARD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`EMMC_IRPT_MASK_INT_A`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`EMMC_IRPT_MASK_INT_B`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`EMMC_IRPT_MASK_INT_C`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`EMMC_IRPT_MASK_RETUNE`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`EMMC_IRPT_MASK_BOOTACK`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`EMMC_IRPT_MASK_ENDBOOT`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`EMMC_IRPT_MASK_CTO_ERR`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`EMMC_IRPT_MASK_CCRC_ERR`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`EMMC_IRPT_MASK_CEND_ERR`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_IRPT_MASK_CBAD_ERR`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_IRPT_MASK_DTO_ERR`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`EMMC_IRPT_MASK_DCRC_ERR`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_IRPT_MASK_DEND_ERR`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`EMMC_IRPT_MASK_SDOFF_ERR`	23	23	`0x00800000`	`0xff7fffff`	`0x0`
`EMMC_IRPT_MASK_ACMD_ERR`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_IRPT_MASK_ADMA_ERR`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`missing definiton`	26	27	`NA`	`NA`	`NA`
`EMMC_IRPT_MASK_DMA_ERR`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`EMMC_IRPT_MASK_ATA_ERR`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`EMMC_IRPT_MASK_OEM_ERR`	30	31	`0xc0000000`	`0x3fffffff`	`0x0`

EMMC_IRPT_EN

Info

Name	value	description
address	`0x7e300038`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_IRPT_EN_CMD_DONE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_IRPT_EN_DATA_DONE`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_IRPT_EN_BLOCK_GAP`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_IRPT_EN_DMA`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`EMMC_IRPT_EN_WRITE_RDY`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`EMMC_IRPT_EN_READ_RDY`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`EMMC_IRPT_EN_CARD_IN`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`EMMC_IRPT_EN_CARD_OUT`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`EMMC_IRPT_EN_CARD`	8	8	`0x00000100`	`0xfffffeff`	`0x0`
`EMMC_IRPT_EN_INT_A`	9	9	`0x00000200`	`0xfffffdff`	`0x0`
`EMMC_IRPT_EN_INT_B`	10	10	`0x00000400`	`0xfffffbff`	`0x0`
`EMMC_IRPT_EN_INT_C`	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
`EMMC_IRPT_EN_RETUNE`	12	12	`0x00001000`	`0xffffefff`	`0x0`
`EMMC_IRPT_EN_BOOTACK`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`EMMC_IRPT_EN_ENDBOOT`	14	14	`0x00004000`	`0xffffbfff`	`0x0`
`missing definiton`	15	15	`NA`	`NA`	`NA`
`EMMC_IRPT_EN_CTO_ERR`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`EMMC_IRPT_EN_CCRC_ERR`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`EMMC_IRPT_EN_CEND_ERR`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_IRPT_EN_CBAD_ERR`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_IRPT_EN_DTO_ERR`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`EMMC_IRPT_EN_DCRC_ERR`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_IRPT_EN_DEND_ERR`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`EMMC_IRPT_EN_SDOFF_ERR`	23	23	`0x00800000`	`0xff7fffff`	`0x0`
`EMMC_IRPT_EN_ACMD_ERR`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_IRPT_EN_ADMA_ERR`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`EMMC_IRPT_EN_TUNE_ERR`	26	26	`0x04000000`	`0xfbffffff`	`0x0`
`missing definiton`	27	27	`NA`	`NA`	`NA`
`EMMC_IRPT_EN_DMA_ERR`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`EMMC_IRPT_EN_ATA_ERR`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`EMMC_IRPT_EN_OEM_ERR`	30	31	`0xc0000000`	`0x3fffffff`	`0x0`

EMMC_CONTROL2

Info

Name	value	description
address	`0x7e30003c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_CONTROL2_ACNOX_ERR`	0	0	`0x00000001`	`0xfffffffe`	`0x0`
`EMMC_CONTROL2_ACTO_ERR`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_CONTROL2_ACCRC_ERR`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_CONTROL2_ACEND_ERR`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`EMMC_CONTROL2_ACBAD_ERR`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`missing definiton`	5	6	`NA`	`NA`	`NA`
`EMMC_CONTROL2_NOTC12_ERR`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`missing definiton`	8	15	`NA`	`NA`	`NA`
`EMMC_CONTROL2_UHSMODE`	16	18	`0x00070000`	`0xfff8ffff`	`0x0`
`EMMC_CONTROL2_SIGTYPE`	19	19	`0x00080000`	`0xfff7ffff`	`0x1`
`EMMC_CONTROL2_DRVTYPE`	20	21	`0x00300000`	`0xffcfffff`	`0x0`
`EMMC_CONTROL2_TUNEON`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`EMMC_CONTROL2_TUNED`	23	23	`0x00800000`	`0xff7fffff`	`0x0`
`missing definiton`	24	29	`NA`	`NA`	`NA`
`EMMC_CONTROL2_EN_AINT`	30	30	`0x40000000`	`0xbfffffff`	`0x0`
`EMMC_CONTROL2_EN_PSV`	31	31	`0x80000000`	`0x7fffffff`	`0x0`

EMMC_HWCAP0

Info

Name	value	description
address	`0x7e300040`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_HWCAP0_TCLKFREQ`	0	5	`0x0000003f`	`0xffffffc0`	`0x0`
`missing definiton`	6	6	`NA`	`NA`	`NA`
`EMMC_HWCAP0_TCLKUNIT`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`EMMC_HWCAP0_BASEMHZ`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`EMMC_HWCAP0_MAXLEN`	16	17	`0x00030000`	`0xfffcffff`	`0x0`
`EMMC_HWCAP0_XMEDBUS`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_HWCAP0_ADMA2`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`missing definiton`	20	20	`NA`	`NA`	`NA`
`EMMC_HWCAP0_HS`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_HWCAP0_SDMA`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`EMMC_HWCAP0_RESUME`	23	23	`0x00800000`	`0xff7fffff`	`0x0`
`EMMC_HWCAP0_V3_3`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_HWCAP0_V3_0`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`EMMC_HWCAP0_V1_8`	26	26	`0x04000000`	`0xfbffffff`	`0x0`
`missing definiton`	27	27	`NA`	`NA`	`NA`
`EMMC_HWCAP0_BUS64`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`EMMC_HWCAP0_AINT`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`EMMC_HWCAP0_SLOT_TYPE`	30	31	`0xc0000000`	`0x3fffffff`	`0x0`

EMMC_HWCAP1

Info

Name	value	description
address	`0x7e300044`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_HWCAP1_SDR50`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`EMMC_HWCAP1_SDR104`	1	1	`0x00000002`	`0xfffffffd`	`0x1`
`EMMC_HWCAP1_DDR50`	2	2	`0x00000004`	`0xfffffffb`	`0x1`
`missing definiton`	3	3	`NA`	`NA`	`NA`
`EMMC_HWCAP1_DRV18_TYPEA`	4	4	`0x00000010`	`0xffffffef`	`0x1`
`EMMC_HWCAP1_DRV18_TYPEC`	5	5	`0x00000020`	`0xffffffdf`	`0x1`
`EMMC_HWCAP1_DRV18_TYPED`	6	6	`0x00000040`	`0xffffffbf`	`0x1`
`missing definiton`	7	7	`NA`	`NA`	`NA`
`EMMC_HWCAP1_RETUNE_TMR`	8	11	`0x00000f00`	`0xfffff0ff`	`0x7`
`missing definiton`	12	12	`NA`	`NA`	`NA`
`EMMC_HWCAP1_SDR50_TUNE`	13	13	`0x00002000`	`0xffffdfff`	`0x0`
`EMMC_HWCAP1_DATA_RETUNE`	14	15	`0x0000c000`	`0xffff3fff`	`0x0`
`EMMC_HWCAP1_MULTIPLIER`	16	23	`0x00ff0000`	`0xff00ffff`	`0x0`
`EMMC_HWCAP1_SPI_MODE`	24	24	`0x01000000`	`0xfeffffff`	`0x1`
`EMMC_HWCAP1_SPI_BLOCKMODE`	25	25	`0x02000000`	`0xfdffffff`	`0x1`

EMMC_HWMAXAMP0

Info

Name	value	description
address	`0x7e300048`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_HWMAXAMP0_AMP_33V`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`EMMC_HWMAXAMP0_AMP_30V`	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
`EMMC_HWMAXAMP0_AMP_18V`	16	23	`0x00ff0000`	`0xff00ffff`	`0x0`

EMMC_FORCE_IRPT

Info

Name	value	description
address	`0x7e300050`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_FORCE_IRPT_CMD_DONE`	0	0	`0x00000001`	`0xfffffffe`	`0x1`
`EMMC_FORCE_IRPT_DATA_DONE`	1	1	`0x00000002`	`0xfffffffd`	`0x0`
`EMMC_FORCE_IRPT_BLOCK_GAP`	2	2	`0x00000004`	`0xfffffffb`	`0x0`
`EMMC_FORCE_IRPT_DMA`	3	3	`0x00000008`	`0xfffffff7`	`0x0`
`EMMC_FORCE_IRPT_WRITE_RDY`	4	4	`0x00000010`	`0xffffffef`	`0x0`
`EMMC_FORCE_IRPT_READ_RDY`	5	5	`0x00000020`	`0xffffffdf`	`0x0`
`EMMC_FORCE_IRPT_CARD_IN`	6	6	`0x00000040`	`0xffffffbf`	`0x0`
`EMMC_FORCE_IRPT_CARD_OUT`	7	7	`0x00000080`	`0xffffff7f`	`0x0`
`missing definiton`	8	15	`NA`	`NA`	`NA`
`EMMC_FORCE_IRPT_CTO_ERR`	16	16	`0x00010000`	`0xfffeffff`	`0x0`
`EMMC_FORCE_IRPT_CCRC_ERR`	17	17	`0x00020000`	`0xfffdffff`	`0x0`
`EMMC_FORCE_IRPT_CEND_ERR`	18	18	`0x00040000`	`0xfffbffff`	`0x0`
`EMMC_FORCE_IRPT_CBAD_ERR`	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
`EMMC_FORCE_IRPT_DTO_ERR`	20	20	`0x00100000`	`0xffefffff`	`0x0`
`EMMC_FORCE_IRPT_DCRC_ERR`	21	21	`0x00200000`	`0xffdfffff`	`0x0`
`EMMC_FORCE_IRPT_DEND_ERR`	22	22	`0x00400000`	`0xffbfffff`	`0x0`
`EMMC_FORCE_IRPT_SDOFF_ERR`	23	23	`0x00800000`	`0xff7fffff`	`0x0`
`EMMC_FORCE_IRPT_ACMD_ERR`	24	24	`0x01000000`	`0xfeffffff`	`0x0`
`EMMC_FORCE_IRPT_ADMA_ERR`	25	25	`0x02000000`	`0xfdffffff`	`0x0`
`EMMC_FORCE_IRPT_TUNE_ERR`	26	26	`0x04000000`	`0xfbffffff`	`0x0`
`missing definiton`	27	27	`NA`	`NA`	`NA`
`EMMC_FORCE_IRPT_DMA_ERR`	28	28	`0x10000000`	`0xefffffff`	`0x0`
`EMMC_FORCE_IRPT_ATA_ERR`	29	29	`0x20000000`	`0xdfffffff`	`0x0`
`EMMC_FORCE_IRPT_OEM_ERR`	30	31	`0xc0000000`	`0x3fffffff`	`0x0`

EMMC_DMA_STATUS

Info

Name	value	description
address	`0x7e300054`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_DMA_STATUS_ERR_AT`	0	1	`0x00000003`	`0xfffffffc`	`0x0`
`EMMC_DMA_STATUS_LEN_NOMATCH`	2	2	`0x00000004`	`0xfffffffb`	`0x0`

EMMC_BOOT_TIMEOUT

Info

Name	value	description
address	`0x7e300070`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_BOOT_TIMEOUT_TIMEOUT`	0	31	`0xffffffff`	`0x00000000`	`0x0`

EMMC_DBG_SEL

Info

Name	value	description
address	`0x7e300074`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_DBG_SEL_SELECT`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

EMMC_EXRDFIFO_CFG

Info

Name	value	description
address	`0x7e300080`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_EXRDFIFO_CFG_RD_THRSH`	0	2	`0x00000007`	`0xfffffff8`	`0x0`

EMMC_EXRDFIFO_EN

Info

Name	value	description
address	`0x7e300084`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_EXRDFIFO_EN_ENABLE`	0	0	`0x00000001`	`0xfffffffe`	`0x0`

EMMC_TUNE_STEP

Info

Name	value	description
address	`0x7e300088`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_TUNE_STEP_DELAY`	0	2	`0x00000007`	`0xfffffff8`	`0x0`

EMMC_TUNE_STEPS_STD

Info

Name	value	description
address	`0x7e30008c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_TUNE_STEPS_STD_STEPS`	0	5	`0x0000003f`	`0xffffffc0`	`0x0`

EMMC_TUNE_STEPS_DDR

Info

Name	value	description
address	`0x7e300090`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_TUNE_STEPS_DDR_STEPS`	0	5	`0x0000003f`	`0xffffffc0`	`0x0`

EMMC_BUS_CTRL

Info

Name	value	description
address	`0x7e3000e0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_BUS_CTRL_CLK_PINS`	0	2	`0x00000007`	`0xfffffff8`	`0x0`
`EMMC_BUS_CTRL_IRQ_PINS`	3	5	`0x00000038`	`0xffffffc7`	`0x0`
`missing definiton`	6	7	`NA`	`NA`	`NA`
`EMMC_BUS_CTRL_BUS_WIDTH`	8	14	`0x00007f00`	`0xffff80ff`	`0x0`
`missing definiton`	15	19	`NA`	`NA`	`NA`
`EMMC_BUS_CTRL_IRQSEL`	20	22	`0x00700000`	`0xff8fffff`	`0x0`
`missing definiton`	23	23	`NA`	`NA`	`NA`
`EMMC_BUS_CTRL_BE_PWR`	24	30	`0x7f000000`	`0x80ffffff`	`0x0`

EMMC_SPI_INT_SPT

Info

Name	value	description
address	`0x7e3000f0`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`EMMC_SPI_INT_SPT_SELECT`	0	7	`0x000000ff`	`0xffffff00`	`0x0`

EMMC_SLOTISR_VER

Info

Name	value	description
address	`0x7e3000fc`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`EMMC_SLOTISR_VER_SLOT_STATUS`	0	7	`0x000000ff`	`0xffffff00`	`0x0`
`missing definiton`	8	15	`NA`	`NA`	`NA`
`EMMC_SLOTISR_VER_SDVERSION`	16	23	`0x00ff0000`	`0xff00ffff`	`0x2`
`EMMC_SLOTISR_VER_VENDOR`	24	31	`0xff000000`	`0x00ffffff`	`0x99`

FPGA

Description

TODO

Info

Name	value	description
base	`0x7e20b600`
id	`0x66706761`

unknown defined macro

define	type	description
`FPGA_CTRL0_OFFSET`	0x08
`FPGA_STATUS0_OFFSET`	0x0C

Registers

name	address	type	width	mask
`FPGA_VERSION`	`0x7e20b600`	RO	32	`0xffffffff`
`FPGA_SCRATCH`	`0x7e20b604`	RW	32	`0xffffffff`
`FPGA_CTRL0`	`0x7e20b608`	RW	36	`0xfffff3fff`
`FPGA_STATUS0`	`0x7e20b60c`	RO	32	`0xfff800ff`
`FPGA_DCM_WR_DATA`	`0x7e20b610`	RW	24	`0x00ffffff`
`FPGA_DCM_CTRL`	`0x7e20b614`	RW	32	`0xff0fffff`
`FPGA_DCM_RD_DATA`	`0x7e20b618`	RO	16	`0x0000ffff`

Register details

FPGA_CTRL0

Info

Name	value	description
address	`0x7e20b608`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`FPGA_CTRL0_DIS_CTL0`	0	0	`0x00000001`	`0xfffffffe`
`FPGA_CTRL0_CAM_CTL0`	0	0	`0x00000001`	`0xfffffffe`
`FPGA_CTRL0_DIS_BL`	1	1	`0x00000002`	`0xfffffffd`
`FPGA_CTRL0_CAM_CTL1`	1	1	`0x00000002`	`0xfffffffd`
`missing definiton`	1	-1	`NA`	`NA`	`NA`
`FPGA_CTRL0_CAM_CTL2`	2	2	`0x00000004`	`0xfffffffb`
`missing definiton`	2	0	`NA`	`NA`	`NA`
`FPGA_CTRL0_DIS_CTL2`	2	2	`0x00000004`	`0xfffffffb`
`missing definiton`	3	1	`NA`	`NA`	`NA`
`FPGA_CTRL0_DIS_RST`	3	3	`0x00000008`	`0xfffffff7`
`FPGA_CTRL0_SD_PSU_EN`	4	4	`0x00000010`	`0xffffffef`
`FPGA_CTRL0_DIS_SW_SPI`	5	5	`0x00000020`	`0xffffffdf`
`FPGA_CTRL0_SW_SPI_SCL`	6	6	`0x00000040`	`0xffffffbf`
`FPGA_CTRL0_SW_SPI_SDA_O`	7	7	`0x00000080`	`0xffffff7f`
`FPGA_CTRL0_SW_SPI_CS`	8	8	`0x00000100`	`0xfffffeff`
`FPGA_CTRL0_SPI0_SEL_A`	9	9	`0x00000200`	`0xfffffdff`
`FPGA_CTRL0_SPI1_SEL`	10	10	`0x00000400`	`0xfffffbff`
`FPGA_CTRL0_DISP_BUFFER`	11	11	`0x00000800`	`0xfffff7ff`
`FPGA_CTRL0_SPI0_SEL_B`	12	12	`0x00001000`	`0xffffefff`
`FPGA_CTRL0_TV_ACTIVITY`	13	13	`0x00002000`	`0xffffdfff`
`missing definiton`	14	15	`NA`	`NA`	`NA`
`FPGA_CTRL0_TERMEN_DO`	16	16	`0x00010000`	`0xfffeffff`
`FPGA_CTRL0_TERMEN_CLK`	17	17	`0x00020000`	`0xfffdffff`
`FPGA_CTRL0_LV_SPARE_OUT`	18	19	`0x000c0000`	`0xfff3ffff`
`FPGA_CTRL0_SPARE_OUT`	20	31	`0xfff00000`	`0x000fffff`

FPGA_STATUS0

Info

Name	value	description
address	`0x7e20b60c`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`FPGA_STATUS0_HW_ID`	0	3	`0x0000000f`	`0xfffffff0`
`FPGA_STATUS0_SD_WP`	4	4	`0x00000010`	`0xffffffef`
`FPGA_STATUS0_SD_CD`	5	5	`0x00000020`	`0xffffffdf`
`FPGA_STATUS0_NAND_RNB`	6	6	`0x00000040`	`0xffffffbf`
`FPGA_STATUS0_SW_SPI_SPI_IN`	7	7	`0x00000080`	`0xffffff7f`
`missing definiton`	8	18	`NA`	`NA`	`NA`
`FPGA_STATUS0_SPARE_IN`	19	31	`0xfff80000`	`0x0007ffff`

FPGA_DCM_WR_DATA

Info

Name	value	description
address	`0x7e20b610`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`FPGA_DCM_WR_DATA_DATA`	0	15	`0x0000ffff`	`0xffff0000`
`FPGA_DCM_WR_DATA_ADDRESS`	16	23	`0x00ff0000`	`0xff00ffff`

FPGA_DCM_CTRL

Info

Name	value	description
address	`0x7e20b614`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset
`FPGA_DCM_CTRL_REMOTE_RST`	0	4	`0x0000001f`	`0xffffffe0`
`missing definiton`	5	7	`NA`	`NA`	`NA`
`FPGA_DCM_CTRL_REMOTE_EN`	8	12	`0x00001f00`	`0xffffe0ff`
`missing definiton`	13	15	`NA`	`NA`	`NA`
`FPGA_DCM_CTRL_PERI_RST`	16	19	`0x000f0000`	`0xfff0ffff`
`missing definiton`	20	23	`NA`	`NA`	`NA`
`FPGA_DCM_CTRL_PERI_EN`	24	27	`0x0f000000`	`0xf0ffffff`
`FPGA_DCM_CTRL_PERI_WR_EN`	28	31	`0xf0000000`	`0x0fffffff`

FPGA_DCM_RD_DATA

Info

Name	value	description
address	`0x7e20b618`

Description

TODO

bits in register

field_name	start_bit	end_bit	set	clear	reset	description
`FPGA_DCM_RD_DATA_DATA`	0	15	`0x0000ffff`	`0xffff0000`

FPGA_A0

Description

TODO

Info

Name	value	description
base	`0x7e213000`

Registers

name	address	type	width	mask	reset	description

Register details

FPGA_B0

Description

TODO

Info

Name	value	description
base	`0x7e214000`

Registers

name	address	type	width	mask	reset	description

Register details

FPGA_MB

Description

TODO

Info

Name	value	description
base	`0x7e20b700`

Registers

name	address	type	width	mask
`FPGA_MB_XSYS_BUILD_NUM`	`0x7e20b700`	RO	32	`0xffffffff`
`FPGA_MB_XC0_BUILD_NUM`	`0x7e20b704`	RO	32	`0xffffffff`
`FPGA_MB_XC1_BUILD_NUM`	`0x7e20b708`	RO	32	`0xffffffff`
`FPGA_MB_XPERI_BUILD_NUM`	`0x7e20b70c`	RO	32	`0xffffffff`
`FPGA_MB_XH264_BUILD_NUM`	`0x7e20b710`	RO	32	`0xffffffff`
`FPGA_MB_XV3D_BUILD_NUM`	`0x7e20b714`	RO	32	`0xffffffff`
`FPGA_MB_XSLC1_BUILD_NUM`	`0x7e20b718`	RO	32	`0xffffffff`
`FPGA_MB_XSLC2_BUILD_NUM`	`0x7e20b71c`	RO	32	`0xffffffff`
`FPGA_MB_XSLC3_BUILD_NUM`	`0x7e20b720`	RO	32	`0xffffffff`
`FPGA_MB_CORE_CLK_FREQ`	`0x7e20b724`	RO	32	`0xffffffff`
`FPGA_MB_SDC_CLK_FREQ`	`0x7e20b728`	RO	32	`0xffffffff`
`FPGA_MB_SDC_H264_FREQ`	`0x7e20b72c`	RO	32	`0xffffffff`
`FPGA_MB_SDC_V3D_FREQ`	`0x7e20b730`	RO	32	`0xffffffff`
`FPGA_MB_SDC_ISP_FREQ`	`0x7e20b734`	RO	32	`0xffffffff`

Register details

GP

Description

TODO

Info

Name	value	description
base	`0x7e200000`
id	`0x6770696f`

Registers

name	address	type	width	mask	reset
`GP_FSEL0`	`0x7e200000`	RW	30	`0x3fffffff`	`0000000000`
`GP_FSEL1`	`0x7e200004`	RW	30	`0x3fffffff`	`0000000000`
`GP_FSEL2`	`0x7e200008`	RW	30	`0x3fffffff`	`0000000000`
`GP_FSEL3`	`0x7e20000c`	RW	30	`0x3fffffff`	`0000000000`
`GP_FSEL4`	`0x7e200010`	RW	30	`0x3fffffff`	`0000000000`
`GP_FSEL5`	`0x7e200014`	RW	30	`0x3fffffff`	`0000000000`
`GP_FSEL6`	`0x7e200018`	RW	30	`0x3fffffff`	`0000000000`
`GP_SET0`	`0x7e20001c`	RW	32	`0xffffffff`	`0000000000`
`GP_SET1`	`0x7e200020`	RW	32	`0xffffffff`	`0000000000`
`GP_SET2`	`0x7e200024`	RW	6	`0x0000003f`	`0000000000`
`GP_CLR0`	`0x7e200028`	RW	32	`0xffffffff`	`0000000000`
`GP_CLR1`	`0x7e20002c`	RW	32	`0xffffffff`	`0000000000`
`GP_CLR2`	`0x7e200030`	RW	6	`0x0000003f`	`0000000000`
`GP_LEV0`	`0x7e200034`	RO	32	`0xffffffff`	`0000000000`
`GP_LEV1`	`0x7e200038`	RO	32	`0xffffffff`	`0000000000`
`GP_LEV2`	`0x7e20003c`	RO	6	`0x0000003f`	`0000000000`
`GP_EDS0`	`0x7e200040`	RW	32	`0xffffffff`	`0000000000`
`GP_EDS1`	`0x7e200044`	RW	32	`0xffffffff`	`0000000000`
`GP_EDS2`	`0x7e200048`	RW	6	`0x0000003f`	`0000000000`
`GP_REN0`	`0x7e20004c`	RW	32	`0xffffffff`	`0000000000`
`GP_REN1`

BCM2835 registers

Preamble

Register Regions

Unknown Definitions

Register Regions

A2W

Description

Info

Registers

Register details

A2W_PLLA_CTRL

Info

Description

bits in register

A2W_PLLA_ANA_SSCS

Info

Description

bits in register

A2W_PLLC_CTRL

Info

Description

bits in register

A2W_PLLC_ANA_SSCS

Info

Description

bits in register

A2W_PLLD_CTRL

Info

Description

bits in register

A2W_PLLD_ANA_SSCS

Info

Description

bits in register

A2W_PLLH_CTRL

Info

Description

bits in register

A2W_HDMI_CTL_RCAL

Info

Description

bits in register

A2W_XOSC_CTRL

Info

Description

bits in register

A2W_SMPS_A_MODE

Info

Description

bits in register

A2W_SMPS_B_STAT

Info

Description

bits in register

A2W_SMPS_C_CLK

Info

Description

bits in register

A2W_SMPS_L_SPV

Info

Description

bits in register

A2W_PLLB_CTRL

Info

Description

bits in register

A2W_PLLB_ANA_SSCS

Info

Description

bits in register

A2W_PLLA_FRAC

Info

Description

bits in register

A2W_PLLA_ANA_SSCL

Info

Description

bits in register

A2W_PLLC_FRAC

Info